/ simplessi.vhd
simplessi.vhd
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 -- 6 -- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics 7 -- http://www.mesanet.com 8 -- 9 -- This program is is licensed under a disjunctive dual license giving you 10 -- the choice of one of the two following sets of free software/open source 11 -- licensing terms: 12 -- 13 -- * GNU General Public License (GPL), version 2.0 or later 14 -- * 3-clause BSD License 15 -- 16 -- 17 -- The GNU GPL License: 18 -- 19 -- This program is free software; you can redistribute it and/or modify 20 -- it under the terms of the GNU General Public License as published by 21 -- the Free Software Foundation; either version 2 of the License, or 22 -- (at your option) any later version. 23 -- 24 -- This program is distributed in the hope that it will be useful, 25 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 26 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 -- GNU General Public License for more details. 28 -- 29 -- You should have received a copy of the GNU General Public License 30 -- along with this program; if not, write to the Free Software 31 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 32 -- 33 -- 34 -- The 3-clause BSD License: 35 -- 36 -- Redistribution and use in source and binary forms, with or without 37 -- modification, are permitted provided that the following conditions 38 -- are met: 39 -- 40 -- * Redistributions of source code must retain the above copyright 41 -- notice, this list of conditions and the following disclaimer. 42 -- 43 -- * Redistributions in binary form must reproduce the above 44 -- copyright notice, this list of conditions and the following 45 -- disclaimer in the documentation and/or other materials 46 -- provided with the distribution. 47 -- 48 -- * Neither the name of Mesa Electronics nor the names of its 49 -- contributors may be used to endorse or promote products 50 -- derived from this software without specific prior written 51 -- permission. 52 -- 53 -- 54 -- Disclaimer: 55 -- 56 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 59 -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 60 -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 61 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 62 -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 63 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 64 -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 66 -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 -- POSSIBILITY OF SUCH DAMAGE. 68 -- 69 70 entity SimpleSSI is 71 Port ( clk : in std_logic; 72 ibus : in std_logic_vector(31 downto 0); 73 obus : out std_logic_vector(31 downto 0); 74 loadcontrol : in std_logic; 75 lstart : in std_logic; 76 pstart : in std_logic; 77 timers : in std_logic_vector(4 downto 0); 78 readdata0 : in std_logic; 79 readdata1 : in std_logic; 80 readcontrol : in std_logic; 81 busyout : out std_logic; 82 davout : out std_logic; 83 ssiclk : out std_logic; 84 ssidata : in std_logic 85 ); 86 end SimpleSSI; 87 88 architecture Behavioral of SimpleSSI is 89 90 91 signal BitrateDDSReg : std_logic_vector(15 downto 0); 92 signal BitrateDDSAccum : std_logic_vector(15 downto 0); 93 alias DDSMSB : std_logic is BitrateDDSAccum(15); 94 signal OldDDSMSB: std_logic; 95 signal BitcountReg : std_logic_vector(6 downto 0); 96 signal BitCount : std_logic_vector(6 downto 0); 97 signal SkewReg : std_logic_vector(3 downto 0); 98 signal SSISreg: std_logic_vector(63 downto 0); 99 signal SSILatch: std_logic_vector(63 downto 0); 100 signal Go: std_logic; 101 signal Start: std_logic; 102 signal BitZero: std_logic; 103 signal OldBitZero: std_logic; 104 signal PStartmask: std_logic; 105 signal TStartmask: std_logic; 106 signal TimerSelect: std_logic_vector(2 downto 0); 107 signal Timer: std_logic; 108 signal OldTimer: std_logic; 109 signal TStart: std_logic; 110 111 signal MaskFirst: std_logic; 112 signal SampleTime: std_logic; 113 signal DAV: std_logic; 114 115 begin 116 117 assiinterface: process (clk,go,lstart,pstartmask,tstartmask,bitcountreg, 118 readdata0,readdata1,ssilatch,readcontrol,Timer,Timers, 119 OldTimer,TimerSelect,TStart,PStart,OldDDSMSB, 120 BitRateDDSAccum,DAv,BitRateDDSReg) 121 begin 122 if clk'event and clk = '1' then 123 124 if Start = '1' then 125 BitCount <= BitCountReg; 126 Go <= '1'; 127 SSISreg <= (Others => '0'); 128 MaskFirst <= '0'; 129 BitZero <= '0'; 130 end if; 131 132 if Go = '1' then 133 BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg; 134 else 135 BitRateDDSAccum <= (others => '0'); 136 end if; 137 138 if SampleTime = '1' then 139 if MaskFirst = '1' then 140 SSISreg <= SSISreg(62 downto 0) & ssidata; 141 end if; 142 if BitCount /= "0000000" then 143 BitCount <= BitCount -1; 144 MaskFirst <= '1'; -- first clock just latches data so dont shift in 145 end if; 146 if BitCount = "0000001" then 147 BitZero <= '1'; -- at bit count of zero, (delayed count of 1); 148 else 149 BitZero <= '0'; 150 end if; 151 end if; 152 153 if BitZero = '0' and OldBitZero = '1' then 154 Go <= '0'; 155 DAV <= '1'; 156 SSILatch <= SSISReg; 157 end if; 158 159 OldDDSMSB <= DDSMSB; 160 OldBitZero <= BitZero; 161 162 if loadcontrol = '1' then 163 BitCountReg <= ibus(6 downto 0); 164 PStartMask <= ibus(8); 165 TStartMask <= ibus(9); 166 TimerSelect <= ibus(14 downto 12); 167 BitRateDDSReg <= ibus(31 downto 16); 168 end if; 169 OldTimer <= Timer; 170 if readdata0 = '1' then 171 DAV <= '0'; 172 end if; 173 end if; -- clk 174 175 if Timer = '1' and OldTimer = '0' then -- rising edge of selected timer 176 TStart <= '1'; 177 else 178 TStart <= '0'; 179 end if; 180 181 case TimerSelect is 182 when "000" => Timer <= timers(0); 183 when "001" => Timer <= timers(1); 184 when "010" => Timer <= timers(2); 185 when "011" => Timer <= timers(3); 186 when "100" => Timer <= timers(4); 187 when others => Timer <= Timers(0); 188 end case; 189 190 if lstart = '1' or (TStart = '1' and TStartMask = '1') or (pstart = '1' and PStartMask = '1')then 191 Start <= '1'; 192 else 193 Start <= '0'; 194 end if; 195 196 SampleTime <= OldDDSMSB and not DDSMSB; 197 198 obus <= (others => 'Z'); 199 if readdata0 = '1' then 200 obus <= SSILatch(31 downto 0); 201 end if; 202 if readdata1 = '1' then 203 obus <= SSILatch(63 downto 32); 204 end if; 205 206 if readcontrol = '1' then 207 obus(6 downto 0) <= BitCountReg; 208 obus(7) <= '0'; 209 obus(8) <= PStartMask; 210 obus(9) <= TStartMask; 211 obus(10) <= '0'; 212 obus(11) <= Go; 213 obus(14 downto 12) <= TimerSelect; 214 obus(15) <= DAV; 215 obus(31 downto 16) <= BitRateDDSReg; 216 end if; 217 218 ssiclk <= not DDSMSB; -- hold time is guaranteed by two directional propagation delay 219 busyout <= Go or (not DAV); 220 davout <= DAV; 221 end process assiinterface; 222 223 end Behavioral;