1  // This file was auto-generated from NVIDIA official Maxwell definitions.
 2  
 3  namespace Ryujinx.Graphics.Gpu.Engine.GPFifo
 4  {
 5      enum TertOp
 6      {
 7          Grp0IncMethod = 0,
 8          Grp0SetSubDevMask = 1,
 9          Grp0StoreSubDevMask = 2,
10          Grp0UseSubDevMask = 3,
11          Grp2NonIncMethod = Grp0IncMethod,
12      }
13  
14      enum SecOp
15      {
16          Grp0UseTert = 0,
17          IncMethod = 1,
18          Grp2UseTert = 2,
19          NonIncMethod = 3,
20          ImmdDataMethod = 4,
21          OneInc = 5,
22          Reserved6 = 6,
23          EndPbSegment = 7,
24      }
25  
26      struct CompressedMethod
27      {
28  #pragma warning disable CS0649 // Field is never assigned to
29          public uint Method;
30  #pragma warning restore CS0649
31          public readonly int MethodAddressOld => (int)((Method >> 2) & 0x7FF);
32          public readonly int MethodAddress => (int)(Method & 0xFFF);
33          public readonly int SubdeviceMask => (int)((Method >> 4) & 0xFFF);
34          public readonly int MethodSubchannel => (int)((Method >> 13) & 0x7);
35          public readonly TertOp TertOp => (TertOp)((Method >> 16) & 0x3);
36          public readonly int MethodCountOld => (int)((Method >> 18) & 0x7FF);
37          public readonly int MethodCount => (int)((Method >> 16) & 0x1FFF);
38          public readonly int ImmdData => (int)((Method >> 16) & 0x1FFF);
39          public readonly SecOp SecOp => (SecOp)((Method >> 29) & 0x7);
40      }
41  }