1  // This file was auto-generated from NVIDIA official Maxwell definitions.
  2  
  3  using Ryujinx.Common.Memory;
  4  
  5  namespace Ryujinx.Graphics.Gpu.Engine.GPFifo
  6  {
  7      /// <summary>
  8      /// Semaphore operation.
  9      /// </summary>
 10      enum SemaphoredOperation
 11      {
 12          Acquire = 1,
 13          Release = 2,
 14          AcqGeq = 4,
 15          AcqAnd = 8,
 16          Reduction = 16,
 17      }
 18  
 19      /// <summary>
 20      /// Semaphore acquire switch enable.
 21      /// </summary>
 22      enum SemaphoredAcquireSwitch
 23      {
 24          Disabled = 0,
 25          Enabled = 1,
 26      }
 27  
 28      /// <summary>
 29      /// Semaphore release interrupt wait enable.
 30      /// </summary>
 31      enum SemaphoredReleaseWfi
 32      {
 33          En = 0,
 34          Dis = 1,
 35      }
 36  
 37      /// <summary>
 38      /// Semaphore release structure size.
 39      /// </summary>
 40      enum SemaphoredReleaseSize
 41      {
 42          SixteenBytes = 0,
 43          FourBytes = 1,
 44      }
 45  
 46      /// <summary>
 47      /// Semaphore reduction operation.
 48      /// </summary>
 49      enum SemaphoredReduction
 50      {
 51          Min = 0,
 52          Max = 1,
 53          Xor = 2,
 54          And = 3,
 55          Or = 4,
 56          Add = 5,
 57          Inc = 6,
 58          Dec = 7,
 59      }
 60  
 61      /// <summary>
 62      /// Semaphore format.
 63      /// </summary>
 64      enum SemaphoredFormat
 65      {
 66          Signed = 0,
 67          Unsigned = 1,
 68      }
 69  
 70      /// <summary>
 71      /// Memory Translation Lookaside Buffer Page Directory Buffer invalidation.
 72      /// </summary>
 73      enum MemOpCTlbInvalidatePdb
 74      {
 75          One = 0,
 76          All = 1,
 77      }
 78  
 79      /// <summary>
 80      /// Memory Translation Lookaside Buffer GPC invalidation enable.
 81      /// </summary>
 82      enum MemOpCTlbInvalidateGpc
 83      {
 84          Enable = 0,
 85          Disable = 1,
 86      }
 87  
 88      /// <summary>
 89      /// Memory Translation Lookaside Buffer invalidation target.
 90      /// </summary>
 91      enum MemOpCTlbInvalidateTarget
 92      {
 93          VidMem = 0,
 94          SysMemCoherent = 2,
 95          SysMemNoncoherent = 3,
 96      }
 97  
 98      /// <summary>
 99      /// Memory operation.
100      /// </summary>
101      enum MemOpDOperation
102      {
103          Membar = 5,
104          MmuTlbInvalidate = 9,
105          L2PeermemInvalidate = 13,
106          L2SysmemInvalidate = 14,
107          L2CleanComptags = 15,
108          L2FlushDirty = 16,
109      }
110  
111      /// <summary>
112      /// Syncpoint operation.
113      /// </summary>
114      enum SyncpointbOperation
115      {
116          Wait = 0,
117          Incr = 1,
118      }
119  
120      /// <summary>
121      /// Syncpoint wait switch enable.
122      /// </summary>
123      enum SyncpointbWaitSwitch
124      {
125          Dis = 0,
126          En = 1,
127      }
128  
129      /// <summary>
130      /// Wait for interrupt scope.
131      /// </summary>
132      enum WfiScope
133      {
134          CurrentScgType = 0,
135          All = 1,
136      }
137  
138      /// <summary>
139      /// Yield operation.
140      /// </summary>
141      enum YieldOp
142      {
143          Nop = 0,
144          PbdmaTimeslice = 1,
145          RunlistTimeslice = 2,
146          Tsg = 3,
147      }
148  
149      /// <summary>
150      /// General Purpose FIFO class state.
151      /// </summary>
152      struct GPFifoClassState
153      {
154  #pragma warning disable CS0649 // Field is never assigned to
155          public uint SetObject;
156          public readonly int SetObjectNvclass => (int)(SetObject & 0xFFFF);
157          public readonly int SetObjectEngine => (int)((SetObject >> 16) & 0x1F);
158          public uint Illegal;
159          public readonly int IllegalHandle => (int)(Illegal);
160          public uint Nop;
161          public readonly int NopHandle => (int)(Nop);
162          public uint Reserved0C;
163          public uint Semaphorea;
164          public readonly int SemaphoreaOffsetUpper => (int)(Semaphorea & 0xFF);
165          public uint Semaphoreb;
166          public readonly int SemaphorebOffsetLower => (int)((Semaphoreb >> 2) & 0x3FFFFFFF);
167          public uint Semaphorec;
168          public readonly int SemaphorecPayload => (int)(Semaphorec);
169          public uint Semaphored;
170          public readonly SemaphoredOperation SemaphoredOperation => (SemaphoredOperation)(Semaphored & 0x1F);
171          public readonly SemaphoredAcquireSwitch SemaphoredAcquireSwitch => (SemaphoredAcquireSwitch)((Semaphored >> 12) & 0x1);
172          public readonly SemaphoredReleaseWfi SemaphoredReleaseWfi => (SemaphoredReleaseWfi)((Semaphored >> 20) & 0x1);
173          public readonly SemaphoredReleaseSize SemaphoredReleaseSize => (SemaphoredReleaseSize)((Semaphored >> 24) & 0x1);
174          public readonly SemaphoredReduction SemaphoredReduction => (SemaphoredReduction)((Semaphored >> 27) & 0xF);
175          public readonly SemaphoredFormat SemaphoredFormat => (SemaphoredFormat)((Semaphored >> 31) & 0x1);
176          public uint NonStallInterrupt;
177          public readonly int NonStallInterruptHandle => (int)(NonStallInterrupt);
178          public uint FbFlush;
179          public readonly int FbFlushHandle => (int)(FbFlush);
180          public uint Reserved28;
181          public uint Reserved2C;
182          public uint MemOpC;
183          public readonly int MemOpCOperandLow => (int)((MemOpC >> 2) & 0x3FFFFFFF);
184          public readonly MemOpCTlbInvalidatePdb MemOpCTlbInvalidatePdb => (MemOpCTlbInvalidatePdb)(MemOpC & 0x1);
185          public readonly MemOpCTlbInvalidateGpc MemOpCTlbInvalidateGpc => (MemOpCTlbInvalidateGpc)((MemOpC >> 1) & 0x1);
186          public readonly MemOpCTlbInvalidateTarget MemOpCTlbInvalidateTarget => (MemOpCTlbInvalidateTarget)((MemOpC >> 10) & 0x3);
187          public readonly int MemOpCTlbInvalidateAddrLo => (int)((MemOpC >> 12) & 0xFFFFF);
188          public uint MemOpD;
189          public readonly int MemOpDOperandHigh => (int)(MemOpD & 0xFF);
190          public readonly MemOpDOperation MemOpDOperation => (MemOpDOperation)((MemOpD >> 27) & 0x1F);
191          public readonly int MemOpDTlbInvalidateAddrHi => (int)(MemOpD & 0xFF);
192          public uint Reserved38;
193          public uint Reserved3C;
194          public uint Reserved40;
195          public uint Reserved44;
196          public uint Reserved48;
197          public uint Reserved4C;
198          public uint SetReference;
199          public readonly int SetReferenceCount => (int)(SetReference);
200          public uint Reserved54;
201          public uint Reserved58;
202          public uint Reserved5C;
203          public uint Reserved60;
204          public uint Reserved64;
205          public uint Reserved68;
206          public uint Reserved6C;
207          public uint Syncpointa;
208          public readonly int SyncpointaPayload => (int)(Syncpointa);
209          public uint Syncpointb;
210          public readonly SyncpointbOperation SyncpointbOperation => (SyncpointbOperation)(Syncpointb & 0x1);
211          public readonly SyncpointbWaitSwitch SyncpointbWaitSwitch => (SyncpointbWaitSwitch)((Syncpointb >> 4) & 0x1);
212          public readonly int SyncpointbSyncptIndex => (int)((Syncpointb >> 8) & 0xFFF);
213          public uint Wfi;
214          public readonly WfiScope WfiScope => (WfiScope)(Wfi & 0x1);
215          public uint CrcCheck;
216          public readonly int CrcCheckValue => (int)(CrcCheck);
217          public uint Yield;
218          public readonly YieldOp YieldOp => (YieldOp)(Yield & 0x3);
219          // TODO: Eventually move this to per-engine state.
220          public Array31<uint> Reserved84;
221          public uint NoOperation;
222          public uint SetNotifyA;
223          public uint SetNotifyB;
224          public uint Notify;
225          public uint WaitForIdle;
226          public uint LoadMmeInstructionRamPointer;
227          public uint LoadMmeInstructionRam;
228          public uint LoadMmeStartAddressRamPointer;
229          public uint LoadMmeStartAddressRam;
230          public uint SetMmeShadowRamControl;
231  #pragma warning restore CS0649
232      }
233  }