1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  /*
 3   * Early initialization code for RISC-V
 4   */
 5  
 6  #include <arch/encoding.h>
 7  #include <bits.h>
 8  #include <mcall.h>
 9  
10  .section ".text._start", "ax", %progbits
11  
12  .globl _stack
13  .global _estack
14  .globl _start
15  _start:
16  	# The boot ROM may pass the following arguments to coreboot:
17  	#   a0: the value of mhartid
18  	#   a1: a pointer to the flattened devicetree
19  	#
20  	# Preserve only the FDT pointer. We can query mhartid ourselves at any
21  	# time.
22  	#
23  	csrw mscratch, a1
24  
25  	# initialize cache as ram
26  	call cache_as_ram
27  
28  	# initialize stack point for each hart
29  	# and the stack must be page-aligned.
30  	# 0xDEADBEEF used to check stack overflow
31  	csrr a0, mhartid
32  	la   t0, _stack
33  	slli t1, a0, RISCV_PGSHIFT
34  	add  t0, t0, t1
35  	li   t1, 0xDEADBEEF
36  	STORE t1, 0(t0)
37  	li   t1, RISCV_PGSIZE - HLS_SIZE
38  	add  sp, t0, t1
39  
40  	# initialize hart-local storage
41  	csrr a0, mhartid
42  	csrrw a1, mscratch, zero
43  	call hls_init
44  
45  	li   a0, CONFIG_RISCV_WORKING_HARTID
46  	call smp_pause
47  
48  	# initialize entry of interrupt/exception
49  	la t0, trap_entry
50  	csrw mtvec, t0
51  
52  	# clear any pending interrupts
53  	csrwi mip, 0
54  
55  	# set up the mstatus register
56  	call mstatus_init
57  	tail main
58  
59  	// These codes need to be implemented on a specific SoC.
60  	.weak cache_as_ram
61  cache_as_ram:
62  	ret