haswell.h
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _CPU_INTEL_HASWELL_H 4 #define _CPU_INTEL_HASWELL_H 5 6 #include <cpu/cpu.h> 7 #include <stdint.h> 8 9 /* CPU types without stepping */ 10 #define HASWELL_FAMILY_TRAD 0x306c0 11 #define HASWELL_FAMILY_ULT 0x40650 12 #define CRYSTALWELL_FAMILY 0x306c0 13 #define BROADWELL_FAMILY_ULT 0x306d0 14 15 /* Haswell CPUIDs */ 16 #define CPUID_HASWELL_A0 0x306c1 17 #define CPUID_HASWELL_B0 0x306c2 18 #define CPUID_HASWELL_C0 0x306c3 19 20 #define CPUID_HASWELL_ULT_B0 0x40650 21 #define CPUID_HASWELL_ULT_C0 0x40651 22 23 /* Crystalwell CPUIDs */ 24 #define CPUID_CRYSTALWELL_B0 0x40660 25 #define CPUID_CRYSTALWELL_C0 0x40661 26 27 /* Broadwell CPUIDs */ 28 #define CPUID_BROADWELL_C0 0x40671 29 30 #define CPUID_BROADWELL_ULT_C0 0x306d2 31 #define CPUID_BROADWELL_ULT_D0 0x306d3 32 #define CPUID_BROADWELL_ULT_E0 0x306d4 33 34 /* Haswell and Broadwell bus clock is fixed at 100MHz */ 35 #define CPU_BCLK 100 36 37 #define MSR_CORE_THREAD_COUNT 0x35 38 #define MSR_PLATFORM_INFO 0xce 39 #define PLATFORM_INFO_SET_TDP (1 << 29) 40 #define TIMED_MWAIT_SUPPORTED (1 << (37 - 32)) 41 #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 42 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 43 #define MSR_FEATURE_CONFIG 0x13c 44 #define SMM_MCA_CAP_MSR 0x17d 45 #define SMM_CPU_SVRSTR_BIT 57 46 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) 47 #define MSR_FLEX_RATIO 0x194 48 #define FLEX_RATIO_LOCK (1 << 20) 49 #define FLEX_RATIO_EN (1 << 16) 50 #define MSR_TEMPERATURE_TARGET 0x1a2 51 #define MSR_MISC_PWR_MGMT 0x1aa 52 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 53 #define MSR_TURBO_RATIO_LIMIT 0x1ad 54 #define MSR_PRMRR_PHYS_BASE 0x1f4 55 #define MSR_PRMRR_PHYS_MASK 0x1f5 56 #define MSR_POWER_CTL 0x1fc 57 #define MSR_LT_LOCK_MEMORY 0x2e7 58 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 59 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 60 #define SMM_FEATURE_CONTROL_MSR 0x4e0 61 #define SMM_CPU_SAVE_EN (1 << 1) 62 63 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 64 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 65 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 66 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 67 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 68 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 69 #define IRTL_VALID (1 << 15) 70 #define IRTL_1_NS (0 << 10) 71 #define IRTL_32_NS (1 << 10) 72 #define IRTL_1024_NS (2 << 10) 73 #define IRTL_32768_NS (3 << 10) 74 #define IRTL_1048576_NS (4 << 10) 75 #define IRTL_33554432_NS (5 << 10) 76 #define IRTL_RESPONSE_MASK (0x3ff) 77 78 /* Long duration in low dword, short duration in high dword */ 79 #define MSR_PKG_POWER_LIMIT 0x610 80 #define PKG_POWER_LIMIT_MASK 0x7fff 81 #define PKG_POWER_LIMIT_EN (1 << 15) 82 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 83 #define PKG_POWER_LIMIT_TIME_SHIFT 17 84 #define PKG_POWER_LIMIT_TIME_MASK 0x7f 85 86 #define MSR_VR_CURRENT_CONFIG 0x601 87 #define MSR_VR_MISC_CONFIG 0x603 88 #define MSR_PKG_POWER_SKU_UNIT 0x606 89 #define MSR_PKG_POWER_SKU 0x614 90 #define MSR_DDR_RAPL_LIMIT 0x618 91 #define MSR_VR_MISC_CONFIG2 0x636 92 #define MSR_PP0_POWER_LIMIT 0x638 93 #define MSR_PP1_POWER_LIMIT 0x640 94 95 #define MSR_CONFIG_TDP_NOMINAL 0x648 96 #define MSR_CONFIG_TDP_LEVEL1 0x649 97 #define MSR_CONFIG_TDP_LEVEL2 0x64a 98 #define MSR_CONFIG_TDP_CONTROL 0x64b 99 #define MSR_TURBO_ACTIVATION_RATIO 0x64c 100 101 /* SMM save state MSRs */ 102 #define SMBASE_MSR 0xc20 103 #define IEDBASE_MSR 0xc22 104 105 /* MTRR_CAP_MSR bit definitions */ 106 #define SMRR_SUPPORTED (1 << 11) 107 #define PRMRR_SUPPORTED (1 << 12) 108 109 /* Intel suggested latency times in units of 1024ns. */ 110 #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 111 #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 112 #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 113 #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 114 #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 115 #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef 116 117 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ 118 (((1 << ((base) * 5)) * (limit)) / 1000) 119 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ 120 C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ 121 (IRTL_1024_NS >> 10)) 122 123 /* P-state configuration */ 124 #define PSS_MAX_ENTRIES 8 125 #define PSS_RATIO_STEP 2 126 #define PSS_LATENCY_TRANSITION 10 127 #define PSS_LATENCY_BUSMASTER 10 128 129 /* Sanity check config options. */ 130 #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) 131 # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" 132 #endif 133 #if (CONFIG_SMM_TSEG_SIZE < 0x800000) 134 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" 135 #endif 136 #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) 137 # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" 138 #endif 139 #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) 140 # error "CONFIG_IED_REGION_SIZE is not a power of 2" 141 #endif 142 143 /* 144 * List of supported C-states for Haswell and Broadwell. 145 * Only the ULT parts support C8, C9, and C10. 146 */ 147 enum { 148 C_STATE_C0 = 0, 149 C_STATE_C1 = 1, 150 C_STATE_C1E = 2, 151 C_STATE_C3 = 3, 152 C_STATE_C6_SHORT_LAT = 4, 153 C_STATE_C6_LONG_LAT = 5, 154 C_STATE_C7_SHORT_LAT = 6, 155 C_STATE_C7_LONG_LAT = 7, 156 C_STATE_C7S_SHORT_LAT = 8, 157 C_STATE_C7S_LONG_LAT = 9, 158 C_STATE_C8 = 10, 159 C_STATE_C9 = 11, 160 C_STATE_C10 = 12, 161 NUM_C_STATES, 162 }; 163 164 /* Lock MSRs */ 165 void intel_cpu_haswell_finalize_smm(void); 166 167 /* Configure power limits for turbo mode */ 168 void set_power_limits(u8 power_limit_1_time); 169 int cpu_config_tdp_levels(void); 170 171 void set_max_freq(void); 172 173 /* CPU identification */ 174 static inline u32 cpu_family_model(void) 175 { 176 return cpuid_eax(1) & 0x0fff0ff0; 177 } 178 179 static inline u32 cpu_stepping(void) 180 { 181 return cpuid_eax(1) & 0xf; 182 } 183 184 static inline int haswell_is_ult(void) 185 { 186 return CONFIG(INTEL_LYNXPOINT_LP); 187 } 188 189 #endif