haswell_init.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <console/console.h> 4 #include <device/device.h> 5 #include <cpu/cpu.h> 6 #include <cpu/x86/mtrr.h> 7 #include <cpu/x86/msr.h> 8 #include <cpu/x86/mp.h> 9 #include <cpu/intel/microcode.h> 10 #include <cpu/intel/smm_reloc.h> 11 #include <cpu/intel/speedstep.h> 12 #include <cpu/intel/turbo.h> 13 #include <cpu/x86/name.h> 14 #include <delay.h> 15 #include <northbridge/intel/haswell/haswell.h> 16 #include <southbridge/intel/lynxpoint/pch.h> 17 #include <cpu/intel/common/common.h> 18 #include <types.h> 19 #include "haswell.h" 20 #include "chip.h" 21 22 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ 23 static const u8 power_limit_time_sec_to_msr[] = { 24 [0] = 0x00, 25 [1] = 0x0a, 26 [2] = 0x0b, 27 [3] = 0x4b, 28 [4] = 0x0c, 29 [5] = 0x2c, 30 [6] = 0x4c, 31 [7] = 0x6c, 32 [8] = 0x0d, 33 [10] = 0x2d, 34 [12] = 0x4d, 35 [14] = 0x6d, 36 [16] = 0x0e, 37 [20] = 0x2e, 38 [24] = 0x4e, 39 [28] = 0x6e, 40 [32] = 0x0f, 41 [40] = 0x2f, 42 [48] = 0x4f, 43 [56] = 0x6f, 44 [64] = 0x10, 45 [80] = 0x30, 46 [96] = 0x50, 47 [112] = 0x70, 48 [128] = 0x11, 49 }; 50 51 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ 52 static const u8 power_limit_time_msr_to_sec[] = { 53 [0x00] = 0, 54 [0x0a] = 1, 55 [0x0b] = 2, 56 [0x4b] = 3, 57 [0x0c] = 4, 58 [0x2c] = 5, 59 [0x4c] = 6, 60 [0x6c] = 7, 61 [0x0d] = 8, 62 [0x2d] = 10, 63 [0x4d] = 12, 64 [0x6d] = 14, 65 [0x0e] = 16, 66 [0x2e] = 20, 67 [0x4e] = 24, 68 [0x6e] = 28, 69 [0x0f] = 32, 70 [0x2f] = 40, 71 [0x4f] = 48, 72 [0x6f] = 56, 73 [0x10] = 64, 74 [0x30] = 80, 75 [0x50] = 96, 76 [0x70] = 112, 77 [0x11] = 128, 78 }; 79 80 /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate 81 * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly 82 * when a core is woken up. */ 83 static int pcode_ready(void) 84 { 85 int wait_count; 86 const int delay_step = 10; 87 88 wait_count = 0; 89 do { 90 if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) 91 return 0; 92 wait_count += delay_step; 93 udelay(delay_step); 94 } while (wait_count < 1000); 95 96 return -1; 97 } 98 99 static void calibrate_24mhz_bclk(void) 100 { 101 int err_code; 102 103 if (pcode_ready() < 0) { 104 printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); 105 return; 106 } 107 108 /* A non-zero value initiates the PCODE calibration. */ 109 mchbar_write32(BIOS_MAILBOX_DATA, ~0); 110 mchbar_write32(BIOS_MAILBOX_INTERFACE, 111 MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL); 112 113 if (pcode_ready() < 0) { 114 printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); 115 return; 116 } 117 118 err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff; 119 120 printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", 121 err_code); 122 123 /* Read the calibrated value. */ 124 mchbar_write32(BIOS_MAILBOX_INTERFACE, 125 MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION); 126 127 if (pcode_ready() < 0) { 128 printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); 129 return; 130 } 131 132 printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", 133 mchbar_read32(BIOS_MAILBOX_DATA)); 134 } 135 136 static u32 pcode_mailbox_read(u32 command) 137 { 138 if (pcode_ready() < 0) { 139 printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); 140 return 0; 141 } 142 143 /* Send command and start transaction */ 144 mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); 145 146 if (pcode_ready() < 0) { 147 printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); 148 return 0; 149 } 150 151 /* Read mailbox */ 152 return mchbar_read32(BIOS_MAILBOX_DATA); 153 } 154 155 static int pcode_mailbox_write(u32 command, u32 data) 156 { 157 if (pcode_ready() < 0) { 158 printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); 159 return -1; 160 } 161 162 mchbar_write32(BIOS_MAILBOX_DATA, data); 163 164 /* Send command and start transaction */ 165 mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); 166 167 if (pcode_ready() < 0) { 168 printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); 169 return -1; 170 } 171 172 return 0; 173 } 174 175 static struct device *cpu_cluster; 176 177 static void initialize_vr_config(void) 178 { 179 struct cpu_vr_config vr_config = { 0 }; 180 msr_t msr; 181 182 /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ 183 const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info; 184 vr_config = conf->vr_config; 185 186 printk(BIOS_DEBUG, "Initializing VR config.\n"); 187 188 /* Configure VR_CURRENT_CONFIG. */ 189 msr = rdmsr(MSR_VR_CURRENT_CONFIG); 190 /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid 191 * on ULT systems. */ 192 msr.hi &= 0xc0000000; 193 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ 194 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ 195 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ 196 197 if (haswell_is_ult()) 198 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ 199 /* Leave the max instantaneous current limit (12:0) to default. */ 200 wrmsr(MSR_VR_CURRENT_CONFIG, msr); 201 202 /* Configure VR_MISC_CONFIG MSR. */ 203 msr = rdmsr(MSR_VR_MISC_CONFIG); 204 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ 205 msr.hi &= ~(0x3ff << (40 - 32)); 206 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ 207 /* Set IOUT_OFFSET to 0. */ 208 msr.hi &= ~0xff; 209 /* Set exit ramp rate to fast. */ 210 msr.hi |= (1 << (50 - 32)); 211 /* Set entry ramp rate to slow. */ 212 msr.hi &= ~(1 << (51 - 32)); 213 /* Enable decay mode on C-state entry. */ 214 msr.hi |= (1 << (52 - 32)); 215 /* Set the slow ramp rate */ 216 if (haswell_is_ult()) { 217 msr.hi &= ~(0x3 << (53 - 32)); 218 /* Configure the C-state exit ramp rate. */ 219 if (vr_config.slow_ramp_rate_enable) { 220 /* Configured slow ramp rate. */ 221 msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); 222 /* Set exit ramp rate to slow. */ 223 msr.hi &= ~(1 << (50 - 32)); 224 } else { 225 /* Fast ramp rate / 4. */ 226 msr.hi |= (1 << (53 - 32)); 227 } 228 } 229 /* Set MIN_VID (31:24) to allow CPU to have full control. */ 230 msr.lo &= ~0xff000000; 231 msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; 232 wrmsr(MSR_VR_MISC_CONFIG, msr); 233 234 /* Configure VR_MISC_CONFIG2 MSR. */ 235 if (!haswell_is_ult()) 236 return; 237 238 msr = rdmsr(MSR_VR_MISC_CONFIG2); 239 msr.lo &= ~0xffff; 240 /* Allow CPU to control minimum voltage completely (15:8) and 241 set the fast ramp voltage in 10mV steps. */ 242 if (cpu_family_model() == BROADWELL_FAMILY_ULT) 243 msr.lo |= 0x006a; /* 1.56V */ 244 else 245 msr.lo |= 0x006f; /* 1.60V */ 246 wrmsr(MSR_VR_MISC_CONFIG2, msr); 247 248 /* Set C9/C10 VCC Min */ 249 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); 250 } 251 252 static void configure_pch_power_sharing(void) 253 { 254 u32 pch_power, pch_power_ext, pmsync, pmsync2; 255 int i; 256 257 /* Read PCH Power levels from PCODE */ 258 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); 259 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); 260 261 printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", 262 pch_power, pch_power_ext); 263 264 pmsync = RCBA32(PMSYNC_CONFIG); 265 pmsync2 = RCBA32(PMSYNC_CONFIG2); 266 267 /* Program PMSYNC_TPR_CONFIG PCH power limit values 268 * pmsync[0:4] = mailbox[0:5] 269 * pmsync[8:12] = mailbox[6:11] 270 * pmsync[16:20] = mailbox[12:17] 271 */ 272 for (i = 0; i < 3; i++) { 273 u32 level = pch_power & 0x3f; 274 pch_power >>= 6; 275 pmsync &= ~(0x1f << (i * 8)); 276 pmsync |= (level & 0x1f) << (i * 8); 277 } 278 RCBA32(PMSYNC_CONFIG) = pmsync; 279 280 /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values 281 * pmsync2[0:4] = mailbox[23:18] 282 * pmsync2[8:12] = mailbox_ext[6:11] 283 * pmsync2[16:20] = mailbox_ext[12:17] 284 * pmsync2[24:28] = mailbox_ext[18:22] 285 */ 286 pmsync2 &= ~0x1f; 287 pmsync2 |= pch_power & 0x1f; 288 289 for (i = 1; i < 4; i++) { 290 u32 level = pch_power_ext & 0x3f; 291 pch_power_ext >>= 6; 292 pmsync2 &= ~(0x1f << (i * 8)); 293 pmsync2 |= (level & 0x1f) << (i * 8); 294 } 295 RCBA32(PMSYNC_CONFIG2) = pmsync2; 296 } 297 298 int cpu_config_tdp_levels(void) 299 { 300 msr_t platform_info; 301 302 /* Bits 34:33 indicate how many levels supported */ 303 platform_info = rdmsr(MSR_PLATFORM_INFO); 304 return (platform_info.hi >> 1) & 3; 305 } 306 307 /* 308 * Configure processor power limits if possible 309 * This must be done AFTER set of BIOS_RESET_CPL 310 */ 311 void set_power_limits(u8 power_limit_1_time) 312 { 313 msr_t msr = rdmsr(MSR_PLATFORM_INFO); 314 msr_t limit; 315 unsigned int power_unit; 316 unsigned int tdp, min_power, max_power, max_time; 317 u8 power_limit_1_val; 318 319 if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) 320 power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; 321 322 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) 323 return; 324 325 /* Get units */ 326 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); 327 power_unit = 2 << ((msr.lo & 0xf) - 1); 328 329 /* Get power defaults for this SKU */ 330 msr = rdmsr(MSR_PKG_POWER_SKU); 331 tdp = msr.lo & 0x7fff; 332 min_power = (msr.lo >> 16) & 0x7fff; 333 max_power = msr.hi & 0x7fff; 334 max_time = (msr.hi >> 16) & 0x7f; 335 336 printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); 337 338 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) 339 power_limit_1_time = power_limit_time_msr_to_sec[max_time]; 340 341 if (min_power > 0 && tdp < min_power) 342 tdp = min_power; 343 344 if (max_power > 0 && tdp > max_power) 345 tdp = max_power; 346 347 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; 348 349 /* Set long term power limit to TDP */ 350 limit.lo = 0; 351 limit.lo |= tdp & PKG_POWER_LIMIT_MASK; 352 limit.lo |= PKG_POWER_LIMIT_EN; 353 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << 354 PKG_POWER_LIMIT_TIME_SHIFT; 355 356 /* Set short term power limit to 1.25 * TDP */ 357 limit.hi = 0; 358 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; 359 limit.hi |= PKG_POWER_LIMIT_EN; 360 /* Power limit 2 time is only programmable on server SKU */ 361 362 wrmsr(MSR_PKG_POWER_LIMIT, limit); 363 364 /* Set power limit values in MCHBAR as well */ 365 mchbar_write32(MCH_PKG_POWER_LIMIT_LO, limit.lo); 366 mchbar_write32(MCH_PKG_POWER_LIMIT_HI, limit.hi); 367 368 /* Set DDR RAPL power limit by copying from MMIO to MSR */ 369 msr.lo = mchbar_read32(MCH_DDR_POWER_LIMIT_LO); 370 msr.hi = mchbar_read32(MCH_DDR_POWER_LIMIT_HI); 371 wrmsr(MSR_DDR_RAPL_LIMIT, msr); 372 373 /* Use nominal TDP values for CPUs with configurable TDP */ 374 if (cpu_config_tdp_levels()) { 375 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); 376 limit.hi = 0; 377 limit.lo = msr.lo & 0xff; 378 wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); 379 } 380 } 381 382 static void configure_c_states(void) 383 { 384 msr_t msr = rdmsr(MSR_PLATFORM_INFO); 385 386 const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); 387 388 msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); 389 msr.lo |= (1 << 30); // Package c-state Undemotion Enable 390 msr.lo |= (1 << 29); // Package c-state Demotion Enable 391 msr.lo |= (1 << 28); // C1 Auto Undemotion Enable 392 msr.lo |= (1 << 27); // C3 Auto Undemotion Enable 393 msr.lo |= (1 << 26); // C1 Auto Demotion Enable 394 msr.lo |= (1 << 25); // C3 Auto Demotion Enable 395 msr.lo |= (1 << 15); // Lock bits 15:0 396 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection 397 398 if (timed_mwait_capable) 399 msr.lo |= (1 << 31); // Timed MWAIT Enable 400 401 /* The deepest package c-state defaults to factory-configured value. */ 402 wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); 403 404 msr = rdmsr(MSR_MISC_PWR_MGMT); 405 msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination 406 wrmsr(MSR_MISC_PWR_MGMT, msr); 407 408 msr = rdmsr(MSR_POWER_CTL); 409 msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 410 msr.lo |= (1 << 1); // C1E Enable 411 msr.lo |= (1 << 0); // Bi-directional PROCHOT# 412 wrmsr(MSR_POWER_CTL, msr); 413 414 /* C-state Interrupt Response Latency Control 0 - package C3 latency */ 415 msr.hi = 0; 416 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; 417 wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); 418 419 /* C-state Interrupt Response Latency Control 1 */ 420 msr.hi = 0; 421 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; 422 wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); 423 424 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ 425 msr.hi = 0; 426 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; 427 wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); 428 429 /* Only Haswell ULT supports the 3-5 latency response registers */ 430 if (!haswell_is_ult()) 431 return; 432 433 /* C-state Interrupt Response Latency Control 3 - package C8 */ 434 msr.hi = 0; 435 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; 436 wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); 437 438 /* C-state Interrupt Response Latency Control 4 - package C9 */ 439 msr.hi = 0; 440 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; 441 wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); 442 443 /* C-state Interrupt Response Latency Control 5 - package C10 */ 444 msr.hi = 0; 445 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; 446 wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); 447 } 448 449 static void configure_thermal_target(struct device *dev) 450 { 451 /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ 452 struct cpu_intel_haswell_config *conf = dev->upstream->dev->chip_info; 453 msr_t msr; 454 455 /* Set TCC activation offset if supported */ 456 msr = rdmsr(MSR_PLATFORM_INFO); 457 if ((msr.lo & (1 << 30)) && conf->tcc_offset) { 458 msr = rdmsr(MSR_TEMPERATURE_TARGET); 459 msr.lo &= ~(0xf << 24); /* Bits 27:24 */ 460 msr.lo |= (conf->tcc_offset & 0xf) << 24; 461 wrmsr(MSR_TEMPERATURE_TARGET, msr); 462 } 463 } 464 465 static void configure_misc(void) 466 { 467 msr_t msr; 468 469 msr = rdmsr(IA32_MISC_ENABLE); 470 msr.lo |= (1 << 0); /* Fast String enable */ 471 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ 472 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ 473 wrmsr(IA32_MISC_ENABLE, msr); 474 475 /* Disable Thermal interrupts */ 476 msr.lo = 0; 477 msr.hi = 0; 478 wrmsr(IA32_THERM_INTERRUPT, msr); 479 480 /* Enable package critical interrupt only */ 481 msr.lo = 1 << 4; 482 msr.hi = 0; 483 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); 484 } 485 486 static void set_max_ratio(void) 487 { 488 msr_t msr, perf_ctl; 489 490 perf_ctl.hi = 0; 491 492 /* Check for configurable TDP option */ 493 if (get_turbo_state() == TURBO_ENABLED) { 494 msr = rdmsr(MSR_TURBO_RATIO_LIMIT); 495 perf_ctl.lo = (msr.lo & 0xff) << 8; 496 } else if (cpu_config_tdp_levels()) { 497 /* Set to nominal TDP ratio */ 498 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); 499 perf_ctl.lo = (msr.lo & 0xff) << 8; 500 } else { 501 /* Platform Info bits 15:8 give max ratio */ 502 msr = rdmsr(MSR_PLATFORM_INFO); 503 perf_ctl.lo = msr.lo & 0xff00; 504 } 505 wrmsr(IA32_PERF_CTL, perf_ctl); 506 507 printk(BIOS_DEBUG, "CPU: frequency set to %d\n", 508 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); 509 } 510 511 static void configure_mca(void) 512 { 513 msr_t msr; 514 int i; 515 const unsigned int num_banks = mca_get_bank_count(); 516 517 /* Enable all error reporting */ 518 msr.lo = msr.hi = ~0; 519 for (i = 0; i < num_banks; i++) 520 wrmsr(IA32_MC_CTL(i), msr); 521 522 /* TODO(adurbin): This should only be done on a cold boot. Also, some 523 * of these banks are core vs package scope. For now every CPU clears 524 * every bank. */ 525 mca_clear_status(); 526 } 527 528 /* All CPUs including BSP will run the following function. */ 529 static void cpu_core_init(struct device *cpu) 530 { 531 /* Clear out pending MCEs */ 532 configure_mca(); 533 534 enable_lapic_tpr(); 535 536 /* Set virtualization based on Kconfig option */ 537 set_vmx_and_lock(); 538 539 /* Configure C States */ 540 configure_c_states(); 541 542 /* Configure Enhanced SpeedStep and Thermal Sensors */ 543 configure_misc(); 544 545 /* Thermal throttle activation offset */ 546 configure_thermal_target(cpu); 547 548 /* Enable Direct Cache Access */ 549 configure_dca_cap(); 550 551 /* Set energy policy */ 552 set_energy_perf_bias(ENERGY_POLICY_NORMAL); 553 554 /* Enable Turbo */ 555 enable_turbo(); 556 } 557 558 /* MP initialization support. */ 559 static const void *microcode_patch; 560 561 static void pre_mp_init(void) 562 { 563 /* Setup MTRRs based on physical address size. */ 564 x86_setup_mtrrs_with_detect(); 565 x86_mtrr_check(); 566 567 initialize_vr_config(); 568 569 if (!haswell_is_ult()) 570 return; 571 572 calibrate_24mhz_bclk(); 573 configure_pch_power_sharing(); 574 } 575 576 static int get_cpu_count(void) 577 { 578 msr_t msr; 579 unsigned int num_threads; 580 unsigned int num_cores; 581 582 msr = rdmsr(MSR_CORE_THREAD_COUNT); 583 num_threads = (msr.lo >> 0) & 0xffff; 584 num_cores = (msr.lo >> 16) & 0xffff; 585 printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", 586 num_cores, num_threads); 587 588 return num_threads; 589 } 590 591 static void get_microcode_info(const void **microcode, int *parallel) 592 { 593 microcode_patch = intel_microcode_find(); 594 *microcode = microcode_patch; 595 *parallel = 1; 596 } 597 598 static void per_cpu_smm_trigger(void) 599 { 600 /* Relocate the SMM handler. */ 601 smm_relocate(); 602 603 /* After SMM relocation a 2nd microcode load is required. */ 604 intel_microcode_load_unlocked(microcode_patch); 605 } 606 607 static void post_mp_init(void) 608 { 609 /* Set Max Ratio */ 610 set_max_ratio(); 611 612 /* Now that all APs have been relocated as well as the BSP let SMIs 613 * start flowing. */ 614 global_smi_enable(); 615 616 /* Lock down the SMRAM space. */ 617 smm_lock(); 618 } 619 620 static const struct mp_ops mp_ops = { 621 .pre_mp_init = pre_mp_init, 622 .get_cpu_count = get_cpu_count, 623 .get_smm_info = smm_info, 624 .get_microcode_info = get_microcode_info, 625 .pre_mp_smm_init = smm_initialize, 626 .per_cpu_smm_trigger = per_cpu_smm_trigger, 627 .relocation_handler = smm_relocation_handler, 628 .post_mp_init = post_mp_init, 629 }; 630 631 void mp_init_cpus(struct bus *cpu_bus) 632 { 633 cpu_cluster = cpu_bus->dev; 634 /* TODO: Handle mp_init_with_smm failure? */ 635 mp_init_with_smm(cpu_bus, &mp_ops); 636 } 637 638 static struct device_operations cpu_dev_ops = { 639 .init = cpu_core_init, 640 }; 641 642 static const struct cpu_device_id cpu_table[] = { 643 { X86_VENDOR_INTEL, CPUID_HASWELL_A0, CPUID_EXACT_MATCH_MASK }, 644 { X86_VENDOR_INTEL, CPUID_HASWELL_B0, CPUID_EXACT_MATCH_MASK }, 645 { X86_VENDOR_INTEL, CPUID_HASWELL_C0, CPUID_EXACT_MATCH_MASK }, 646 { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0, CPUID_EXACT_MATCH_MASK }, 647 { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0, CPUID_EXACT_MATCH_MASK }, 648 { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0, CPUID_EXACT_MATCH_MASK }, 649 { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0, CPUID_EXACT_MATCH_MASK }, 650 { X86_VENDOR_INTEL, CPUID_BROADWELL_C0, CPUID_EXACT_MATCH_MASK }, 651 { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0, CPUID_EXACT_MATCH_MASK }, 652 { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0, CPUID_EXACT_MATCH_MASK }, 653 { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0, CPUID_EXACT_MATCH_MASK }, 654 CPU_TABLE_END 655 }; 656 657 static const struct cpu_driver driver __cpu_driver = { 658 .ops = &cpu_dev_ops, 659 .id_table = cpu_table, 660 };