model_1067x_init.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <console/console.h> 4 #include <device/device.h> 5 #include <cpu/cpu.h> 6 #include <cpu/x86/msr.h> 7 #include <cpu/intel/speedstep.h> 8 #include <cpu/x86/cache.h> 9 #include <cpu/x86/name.h> 10 #include <cpu/intel/smm_reloc.h> 11 12 #define MSR_BBL_CR_CTL3 0x11e 13 14 static void configure_c_states(const int quad) 15 { 16 msr_t msr; 17 18 /* Is C5 requested and supported? */ 19 const int c5 = southbridge_support_c5() && 20 (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && 21 !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); 22 /* Is C6 requested and supported? */ 23 const int c6 = southbridge_support_c6() && 24 ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; 25 26 const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ 27 28 msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); 29 msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk 30 msr.lo |= (1 << 8); 31 if (quad) 32 msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); 33 if (c5) { 34 msr.lo &= ~(1 << 13); 35 msr.lo &= ~(7 << 0); 36 msr.lo |= (1 << 3); /* Enable dynamic L2. */ 37 msr.lo |= (1 << 14); /* Enable deeper sleep */ 38 } 39 /* Next two fields seem to be mutually exclusive: */ 40 msr.lo &= ~(7 << 4); 41 msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ 42 if (c6) 43 msr.lo |= (1 << 25); 44 wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); 45 46 /* Set Processor MWAIT IO BASE */ 47 msr.hi = 0; 48 msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) 49 << 16); 50 wrmsr(MSR_PMG_IO_BASE_ADDR, msr); 51 52 /* Set IO Capture Address */ 53 msr.hi = 0; 54 msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); 55 wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); 56 57 if (c5) { 58 msr = rdmsr(MSR_BBL_CR_CTL3); 59 msr.lo &= ~(7 << 25); 60 msr.lo |= (2 << 25); 61 msr.lo &= ~(3 << 30); 62 msr.lo |= (1 << 30); 63 wrmsr(MSR_BBL_CR_CTL3, msr); 64 } 65 } 66 67 static void configure_p_states(const char stepping, const char cores) 68 { 69 msr_t msr; 70 71 msr = rdmsr(MSR_EXTENDED_CONFIG); 72 /* Super LFM supported? */ 73 if (northbridge_support_slfm() && (msr.lo & (1 << 27))) 74 msr.lo |= (1 << 28); /* Enable Super LFM. */ 75 wrmsr(MSR_EXTENDED_CONFIG, msr); 76 77 if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { 78 /* Turbo supported? */ 79 if ((stepping == 0xa) && (cores < 4)) { 80 msr = rdmsr(MSR_FSB_FREQ); 81 msr.lo |= (1 << 3); /* Enable hysteresis. */ 82 wrmsr(MSR_FSB_FREQ, msr); 83 } 84 msr = rdmsr(IA32_PERF_CTL); 85 msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ 86 wrmsr(IA32_PERF_CTL, msr); 87 } 88 89 msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); 90 msr.lo &= ~(1 << 11); /* Enable hw coordination. */ 91 msr.lo |= (1 << 15); /* Lock config until next reset. */ 92 wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); 93 } 94 95 #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) 96 #define MSR_EMTTM_TABLE_NUM 6 97 static void configure_emttm_tables(void) 98 { 99 int i; 100 int num_states, pstate_idx; 101 msr_t msr; 102 sst_table_t pstates; 103 104 /* Gather p-state information. */ 105 speedstep_gen_pstates(&pstates); 106 107 /* Never turbo mode or Super LFM. */ 108 num_states = pstates.num_states; 109 if (pstates.states[0].is_turbo) 110 --num_states; 111 if (pstates.states[pstates.num_states - 1].is_slfm) 112 --num_states; 113 /* Repeat lowest p-state if we haven't enough states. */ 114 const int num_lowest_pstate = 115 (num_states < MSR_EMTTM_TABLE_NUM) 116 ? (MSR_EMTTM_TABLE_NUM - num_states) + 1 117 : 1; 118 /* Start from the lowest entry but skip Super LFM. */ 119 if (pstates.states[pstates.num_states - 1].is_slfm) 120 pstate_idx = pstates.num_states - 2; 121 else 122 pstate_idx = pstates.num_states - 1; 123 for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) { 124 if (i >= num_lowest_pstate) 125 --pstate_idx; 126 const sst_state_t *const pstate = &pstates.states[pstate_idx]; 127 printk(BIOS_DEBUG, "writing P-State %d: %d, %d, " 128 "%2d, 0x%02x, %d; encoded: 0x%04x\n", 129 pstate_idx, pstate->dynfsb, pstate->nonint, 130 pstate->ratio, pstate->vid, pstate->power, 131 SPEEDSTEP_ENCODE_STATE(*pstate)); 132 msr.hi = 0; 133 msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) & 134 /* Don't set half ratios. */ 135 ~SPEEDSTEP_RATIO_NONINT; 136 wrmsr(MSR_EMTTM_CR_TABLE(i), msr); 137 } 138 139 msr = rdmsr(MSR_EMTTM_CR_TABLE(5)); 140 msr.lo |= (1 << 31); /* lock tables */ 141 wrmsr(MSR_EMTTM_CR_TABLE(5), msr); 142 } 143 144 #define IA32_PECI_CTL 0x5a0 145 146 static void configure_misc(const int eist, const int tm2, const int emttm) 147 { 148 msr_t msr; 149 150 const u32 sub_cstates = cpuid_edx(5); 151 152 msr = rdmsr(IA32_MISC_ENABLE); 153 msr.lo |= (1 << 3); /* TM1 enable */ 154 if (tm2) 155 msr.lo |= (1 << 13); /* TM2 enable */ 156 msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ 157 msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */ 158 159 msr.lo |= (1 << 10); /* FERR# multiplexing */ 160 161 if (eist) 162 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ 163 164 /* Enable C2E */ 165 if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) 166 msr.lo |= (1 << 26); 167 168 /* Enable C4E */ 169 if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { 170 msr.hi |= (1 << (32 - 32)); // C4E 171 msr.hi |= (1 << (33 - 32)); // Hard C4E 172 } 173 174 /* Enable EMTTM */ 175 if (emttm) 176 msr.hi |= (1 << (36 - 32)); 177 178 /* Enable turbo mode */ 179 if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) 180 msr.hi &= ~(1 << (38 - 32)); 181 182 wrmsr(IA32_MISC_ENABLE, msr); 183 184 if (eist) { 185 msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ 186 wrmsr(IA32_MISC_ENABLE, msr); 187 } 188 189 /* Enable PECI 190 WARNING: due to Erratum AW67 described in Intel document #318733 191 the microcode must be updated before this MSR is written to. */ 192 msr = rdmsr(IA32_PECI_CTL); 193 msr.lo |= 1; 194 wrmsr(IA32_PECI_CTL, msr); 195 } 196 197 #define PIC_SENS_CFG 0x1aa 198 static void configure_pic_thermal_sensors(const int tm2, const int quad) 199 { 200 msr_t msr; 201 202 msr = rdmsr(PIC_SENS_CFG); 203 204 if (quad) 205 msr.lo |= (1 << 31); 206 else 207 msr.lo &= ~(1 << 31); 208 if (tm2) 209 msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */ 210 msr.lo |= (1 << 21); // inter-core lock TM1 211 msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */ 212 213 wrmsr(PIC_SENS_CFG, msr); 214 } 215 216 static void model_1067x_init(struct device *cpu) 217 { 218 char processor_name[49]; 219 220 /* Gather some information: */ 221 222 const struct cpuid_result cpuid1 = cpuid(1); 223 224 /* Read stepping. */ 225 const char stepping = cpuid1.eax & 0xf; 226 /* Read number of cores. */ 227 const char cores = (cpuid1.ebx >> 16) & 0xf; 228 /* Is this a quad core? */ 229 const char quad = cores > 2; 230 /* Is this even a multiprocessor? */ 231 const char mp = cores > 1; 232 233 /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */ 234 const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4); 235 236 /* Is enhanced speedstep supported? */ 237 const char eist = (cpuid1.ecx & (1 << 7)) && 238 !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17)); 239 /* Test for TM2 only if EIST is available. */ 240 const char tm2 = eist && (cpuid1.ecx & (1 << 8)); 241 242 /* Print processor name */ 243 fill_processor_name(processor_name); 244 printk(BIOS_INFO, "CPU: %s.\n", processor_name); 245 246 /* Configure C States */ 247 configure_c_states(quad); 248 249 /* Configure P States */ 250 configure_p_states(stepping, cores); 251 252 /* EMTTM */ 253 if (emttm) 254 configure_emttm_tables(); 255 256 /* Configure Enhanced SpeedStep and Thermal Sensors */ 257 configure_misc(eist, tm2, emttm); 258 259 /* PIC thermal sensor control */ 260 configure_pic_thermal_sensors(tm2, quad); 261 } 262 263 static struct device_operations cpu_dev_ops = { 264 .init = model_1067x_init, 265 }; 266 267 static const struct cpu_device_id cpu_table[] = { 268 { X86_VENDOR_INTEL, 0x10676, CPUID_EXACT_MATCH_MASK }, 269 { X86_VENDOR_INTEL, 0x10677, CPUID_EXACT_MATCH_MASK }, 270 { X86_VENDOR_INTEL, 0x1067A, CPUID_EXACT_MATCH_MASK }, 271 CPU_TABLE_END 272 }; 273 274 static const struct cpu_driver driver __cpu_driver = { 275 .ops = &cpu_dev_ops, 276 .id_table = cpu_table, 277 };