Kconfig
1 ## SPDX-License-Identifier: GPL-2.0-only 2 3 config INTEL_DDI 4 bool 5 default n 6 help 7 helper functions for intel DDI operations 8 9 config INTEL_EDID 10 bool 11 default n 12 13 config INTEL_INT15 14 bool 15 default n 16 17 config INTEL_GMA_ACPI 18 bool 19 default n 20 21 config INTEL_GMA_BCLV_OFFSET 22 hex 23 default 0xc8254 24 25 config INTEL_GMA_BCLV_WIDTH 26 int 27 default 16 28 29 config INTEL_GMA_BCLM_OFFSET 30 hex 31 default 0xc8256 32 33 config INTEL_GMA_BCLM_WIDTH 34 int 35 default 16 36 37 config INTEL_GMA_SSC_ALTERNATE_REF 38 bool 39 default n 40 help 41 Set when the SSC reference clock for LVDS runs at a different fre- 42 quency than the general display reference clock. 43 44 To be set by northbridge or mainboard Kconfig. For most platforms, 45 there is no choice, i.e. for i945 and gm45 the SSC reference always 46 differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz 47 DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's 48 the same frequency for SSC/non-SSC (120MHz). The only, currently 49 supported platform with a choice seems to be Pineview, where the 50 alternative is 100MHz vs. the default 96MHz. 51 52 config INTEL_GMA_SWSMISCI 53 bool 54 default n 55 help 56 Select this option for Atom-based platforms which use the SWSMISCI 57 register (0xe0) rather than the SWSCI register (0xe8). 58 59 config INTEL_GMA_LIBGFXINIT_EDID 60 bool 61 62 config VBT_CBFS_COMPRESSION_DEFAULT_LZ4 63 def_bool n 64 help 65 Set LZ4 VBT compression. 66 67 config VBT_CBFS_COMPRESSION_DEFAULT_NONE 68 def_bool n 69 help 70 Disable VBT compression. 71 72 choice 73 prompt "VBT Compression algorithm" 74 depends on INTEL_GMA_ADD_VBT 75 default VBT_CBFS_COMPRESSION_LZ4 if VBT_CBFS_COMPRESSION_DEFAULT_LZ4 76 default VBT_CBFS_COMPRESSION_NONE if VBT_CBFS_COMPRESSION_DEFAULT_NONE 77 default VBT_CBFS_COMPRESSION_LZMA 78 79 config VBT_CBFS_COMPRESSION_LZMA 80 bool "Compress VBT with LZMA algorithm" 81 82 config VBT_CBFS_COMPRESSION_LZ4 83 bool "Compress VBT with LZ4 algorithm" 84 85 config VBT_CBFS_COMPRESSION_NONE 86 bool "Do not compress VBT" 87 88 endchoice 89 90 config VBT_CBFS_COMPRESSION_ALGORITHM 91 string 92 default "lzma" if VBT_CBFS_COMPRESSION_LZMA 93 default "lz4" if VBT_CBFS_COMPRESSION_LZ4 94 default "none" if VBT_CBFS_COMPRESSION_NONE 95 96 config GFX_GMA_ANALOG_I2C_HDMI_B 97 bool 98 99 config GFX_GMA_ANALOG_I2C_HDMI_C 100 bool 101 102 config GFX_GMA_ANALOG_I2C_HDMI_D 103 bool 104 105 config GFX_GMA_IGNORE_PRESENCE_STRAPS 106 def_bool n 107 depends on MAINBOARD_HAS_LIBGFXINIT 108 help 109 libgfxinit uses the GPU presence straps to determine if a display port 110 is present/enabled. Select this option if a board doesn't correctly implement 111 these straps, causing libgfxinit to fail to detect an attached panel. 112 113 config GFX_GMA 114 def_bool y 115 depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ 116 || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ 117 || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \ 118 || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \ 119 || SOC_INTEL_CANNONLAKE_BASE 120 depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID 121 select RAMSTAGE_LIBHWBASE 122 123 config EARLY_GFX_GMA 124 def_bool y 125 depends on SOC_INTEL_ALDERLAKE 126 depends on MAINBOARD_USE_EARLY_LIBGFXINIT 127 select ROMSTAGE_LIBHWBASE 128 129 config GFX_GMA_DEFAULT_MMIO 130 hex 131 depends on HWBASE_STATIC_MMIO && (GFX_GMA || EARLY_GFX_GMA) 132 help 133 Graphics device MMIO address. This is typically an unused 134 memory mapping region which can be allocated to the MMIO 135 region as graphics PCI device Base Address Range zero. 136 137 config GFX_GMA_PANEL_1_ON_EDP 138 bool 139 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ 140 || MAINBOARD_HAS_EARLY_LIBGFXINIT 141 default n if GFX_GMA_PANEL_1_ON_LVDS 142 default y 143 144 config GFX_GMA_PANEL_1_ON_LVDS 145 bool 146 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ 147 || MAINBOARD_HAS_EARLY_LIBGFXINIT 148 default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE 149 default n 150 151 config INTEL_GMA_OPREGION_2_1 152 bool 153 default n 154 155 config INTEL_GMA_VERSION_2 156 bool 157 default n 158 help 159 Intel display port and pipe related register definitions have changed since 160 Tiger Lake SoC. This option enables support for the updated `TRANS_DDI_FUNC_CTL` 161 register definitions. 162 163 SoCs that support Intel GMA Version 2 include: 164 * Alder Lake 165 * Meteor Lake 166 * Tiger Lake 167 168 If you are unsure whether your SoC supports Intel GMA Version 2, it is safe to 169 disable this option. 170 171 if GFX_GMA || EARLY_GFX_GMA 172 173 config GFX_GMA_DYN_CPU 174 def_bool y 175 help 176 Activates runtime CPU detection in libgfxinit. 177 178 config GFX_GMA_GENERATION 179 string 180 default "Broxton" if SOC_INTEL_APOLLOLAKE 181 default "Skylake" if SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_CANNONLAKE_BASE 182 default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL 183 default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE 184 default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X 185 default "Tigerlake" if SOC_INTEL_ALDERLAKE 186 187 config GFX_GMA_PCH 188 string 189 default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE 190 default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE 191 default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL 192 default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE 193 default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE 194 default "Alder_Point" if SOC_INTEL_ALDERLAKE 195 default "No_PCH" 196 197 config GFX_GMA_PANEL_1_PORT 198 string 199 default "eDP" if GFX_GMA_PANEL_1_ON_EDP 200 default "LVDS" 201 202 config GFX_GMA_PANEL_2_PORT 203 string 204 default "Disabled" 205 206 config GFX_GMA_ANALOG_I2C_PORT 207 string 208 default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B 209 default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C 210 default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D 211 default "PCH_DAC" 212 help 213 Boards with a DVI-I connector share the I2C pins for both analog and 214 digital displays. In that case, the EDID for a VGA display has to be 215 read over the I2C interface of the coupled digital port. 216 217 endif