1  #ifndef GM_H_
 2  #define GM_H_
 3  
 4  #include "hal.h"
 5  
 6  
 7  #define PLX_VENDOR_ID           0x10B5 //PLX Vendor ID
 8  #define GM_DEVICE_ID            0x6ACC //GM 6 Axis Control Card,   www.pcidatabase.com
 9  #define GM_SUBDEVICE_ID_1         0x3131
10  #define GM_SUBDEVICE_ID_2         0x6ACC
11  
12  #define MAX_GM_DEVICES		3
13  
14  #define RS485MODUL_ID_8INPUT 0x1
15  #define RS485MODUL_ID_8OUTPUT 0x2
16  #define RS485MODUL_ID_DACADC 0x3
17  #define RS485MODUL_ID_TEACHPAD 0x04
18  
19  #define IDmask_card 	0xF0000000
20  #define cardVersion1 	0x10000000
21  #define IDmask_can 	0x000F0000
22  #define canVersion1 	0x00010000
23  #define IDmask_rs485 	0x0000F000
24  #define rs485Version1 	0x00001000
25  #define IDmask_dac 	0x00000F00
26  #define dacVersion1 	0x00000100
27  #define dacVersion2 	0x00000200
28  #define IDmask_stepgen 	0x000000F0
29  #define stepgenVersion1 0x00000010
30  #define IDmask_encoder 	0x0000000F
31  #define encoderVersion1 0x00000001
32  #define notPresented	0x00000000
33  
34  typedef struct {
35  	hal_u32_t			serialModulesDataOut[16][8]; // 0000 0000
36  	hal_u32_t			serialModulesDataIn[16][8];  // 1000 0000
37  	
38  	hal_u32_t			moduleId[8];		//addr 0 	0000 000 
39  	
40  	hal_u32_t			card_status_reg;	//addr 1	0001 000        //  ... Estop_2 | Estop_1 | Pwr_fault | Bus_err | Wdt_err  //Card status read resets wdt
41  	hal_u32_t			cardID;				//	0001 001
42  	hal_u32_t			card_control_reg; 		//	0001 010	//  Wdt_period(16 bit)[us] | ... | EstopEn_2 | EstopEn_1 | power_enable | card_enable
43  	hal_u32_t			reserved_0;			//	0001 011
44  	hal_u32_t			gpio;				//	0001 100
45  	hal_u32_t			gpioDir;			//	0001 101
46  	hal_u32_t			StepGen_status;			//	0001 110
47  	hal_u32_t			PCI_clk_counter;		//	0001 111
48  	
49  	hal_u32_t			ENC_control_reg;	//addr 2	0010 000
50  	hal_u32_t			CAN_status_reg;
51  	hal_u32_t			CAN_control_reg;
52  	hal_u32_t			DAC_0; //DAC AXIS 1-0
53  	hal_u32_t			DAC_1; //DAC AXIS 3-2
54  	hal_u32_t			DAC_2; //DAC AXIS 5-4
55  	hal_u32_t			reserved_1[2];
56  	
57  	hal_u32_t			CAN_RX_buffer[4];	//addr 3     	0011 000
58  	hal_u32_t			CAN_TX_buffer[4];	
59  	hal_u32_t			reserved_2[8];		//addr 4       	0100 000
60  		
61  	hal_u32_t			reserved_3[8];		//addr 5       	0101 000
62  		
63  	hal_u32_t			reserved_4[8];		//addr 6       	0110 000
64  	
65  	hal_u32_t			reserved_5[8];		//addr 7       	0111 000
66  	
67  	hal_s32_t			ENC_counter[6];		//addr 8	1000 000
68  	hal_u32_t			reserved_6[2];
69  	hal_s32_t			ENC_period[6];		//addr 9	1001 000
70  	hal_u32_t			reserved_7[2];
71  	hal_s32_t			ENC_index_latch[6]; 	//addr 10	1010 000
72  	hal_u32_t			reserved_8[2];
73  	hal_s32_t			reserved_9[8]; 		//addr 11	1011 000
74  
75  	hal_s32_t			StepGen_steprate[6];	//addr 12	1100 000
76  	hal_u32_t			reserved_10[2];
77  	hal_u32_t			StepGen_fb[6];		//addr 13	1101 000
78  	hal_u32_t			reserved_11[2];			
79  	hal_u32_t			StepGen_time_params[6];	//addr 14	1110 000
80  	hal_u32_t			reserved_12[2];		
81  	hal_u32_t			reserved_16[8];		//addr 15	1111 000
82  
83  } volatile card;
84  
85  
86  
87  #endif
88