1  /* SPDX-License-Identifier: GPL-2.0-only */
  2  
  3  /* This file applies to AMD64 products.
  4   * The definitions come from the AMD64 Programmers Manual vol2
  5   * Revision 3.30 and/or the device's BKDG.
  6   */
  7  
  8  #ifndef CPU_AMD_CPUID_H
  9  #define CPU_AMD_CPUID_H
 10  
 11  #define CPUID_L1_TLB_CACHE_IDS		0x80000005
 12  /* Fn0x80000005_EAX */
 13  #define  L1_DAT_TLB_2M4M_ASSOC_SHFT	24
 14  #define  L1_DAT_TLB_2M4M_ASSOC_MASK	(0xff << L1_DAT_TLB_2M4M_ASSOC_SHFT)
 15  #define  L1_DAT_TLB_2M4M_SIZE_SHFT	16
 16  #define  L1_DAT_TLB_2M4M_SIZE_MASK	(0xff << L1_DAT_TLB_2M4M_SIZE_SHFT)
 17  #define  L1_INST_TLB_2M4M_ASSOC_SHFT	8
 18  #define  L1_INST_TLB_2M4M_ASSOC_MASK	(0xff << L1_INST_TLB_2M4M_ASSOC_SHFT)
 19  #define  L1_INST_TLB_2M4M_SIZE_SHFT	0
 20  #define  L1_INST_TLB_2M4M_SIZE_MASK	(0xff << L1_INST_TLB_2M4M_SIZE_SHFT)
 21  /* Fn0x80000005_EBX */
 22  #define  L1_DAT_TLB_4K_ASSOC_SHFT	24
 23  #define  L1_DAT_TLB_4K_ASSOC_MASK	(0xff << L1_DAT_TLB_4K_ASSOC_SHFT)
 24  #define  L1_DAT_TLB_4K_SIZE_SHFT	16
 25  #define  L1_DAT_TLB_4K_SIZE_MASK	(0xff << L1_DAT_TLB_4K_SIZE_SHFT)
 26  #define  L1_INST_TLB_4K_ASSOC_SHFT	8
 27  #define  L1_INST_TLB_4K_ASSOC_MASK	(0xff << L1_INST_TLB_4K_ASSOC_SHFT)
 28  #define  L1_INST_TLB_4K_SIZE_SHFT	0
 29  #define  L1_INST_TLB_4K_SIZE_MASK	(0xff << L1_INST_TLB_4K_SIZE_SHFT)
 30  /* Fn0x80000005_ECX */
 31  #define  L1_DC_SIZE_SHFT		24
 32  #define  L1_DC_SIZE_MASK		(0xff << L1_DC_SIZE_SHFT)
 33  #define  L1_DC_ASSOC_SHFT		16
 34  #define  L1_DC_ASSOC_MASK		(0xff << L1_DC_ASSOC_SHFT)
 35  #define  L1_DC_LINE_TAG_SHFT		8
 36  #define  L1_DC_LINE_TAG_MASK		(0xff << L1_DC_LINE_TAG_SHFT)
 37  #define  L1_DC_LINE_SIZE_SHFT		0
 38  #define  L1_DC_LINE_SIZE_MASK		(0xff << L1_DC_LINE_SIZE_SHFT)
 39  /* Fn0x80000005_EDX */
 40  #define  L1_IC_SIZE_SHFT		24
 41  #define  L1_IC_SIZE_MASK		(0xff << L1_IC_SIZE_SHFT)
 42  #define  L1_IC_ASSOC_SHFT		16
 43  #define  L1_IC_ASSOC_MASK		(0xff << L1_IC_ASSOC_SHFT)
 44  #define  L1_IC_LINE_TAG_SHFT		8
 45  #define  L1_IC_LINE_TAG_MASK		(0xff << L1_IC_LINE_TAG_SHFT)
 46  #define  L1_IC_LINE_SIZE_SHFT		0
 47  #define  L1_IC_LINE_SIZE_MASK		(0xff << L1_IC_LINE_SIZE_SHFT)
 48  
 49  #define CPUID_L2_L3_CACHE_L2_TLB_IDS	0x80000006
 50  /* Fn0x80000006_EAX */
 51  #define  L2_DAT_TLB_2M4M_ASSOC_SHFT	28
 52  #define  L2_DAT_TLB_2M4M_ASSOC_MASK	(0xf << L2_DAT_TLB_2M4M_ASSOC_SHFT)
 53  #define  L2_DAT_TLB_2M4M_SIZE_SHFT	16
 54  #define  L2_DAT_TLB_2M4M_SIZE_MASK	(0xfff << L2_DAT_TLB_2M4M_SIZE_SHFT)
 55  #define  L2_INST_TLB_2M4M_ASSOC_SHFT	12
 56  #define  L2_INST_TLB_2M4M_ASSOC_MASK	(0xf << L2_INST_TLB_2M4M_ASSOC_SHFT)
 57  #define  L2_INST_TLB_2M4M_SIZE_SHFT	0
 58  #define  L2_INST_TLB_2M4M_SIZE_MASK	(0xfff << L2_INST_TLB_2M4M_SIZE_SHFT)
 59  /*Fn0x80000006_EBX */
 60  #define  L2_DAT_TLB_4K_ASSOC_SHFT	28
 61  #define  L2_DAT_TLB_4K_ASSOC_MASK	(0xf << L2_DAT_TLB_4K_ASSOC_SHFT)
 62  #define  L2_DAT_TLB_4K_SIZE_SHFT	16
 63  #define  L2_DAT_TLB_4K_SIZE_MASK	(0xfff << L2_DAT_TLB_4K_SIZE_SHFT)
 64  #define  L2_INST_TLB_4K_ASSOC_SHFT	12
 65  #define  L2_INST_TLB_4K_ASSOC_MASK	(0xf << L2_INST_TLB_4K_ASSOC_SHFT)
 66  #define  L2_INST_TLB_4K_SIZE_SHFT	0
 67  #define  L2_INST_TLB_4K_SIZE_MASK	(0xfff << L2_INST_TLB_4K_SIZE_SHFT)
 68  /* Fn0x80000006_ECX */
 69  #define  L2_DC_SIZE_SHFT		16
 70  #define  L2_DC_SIZE_MASK		(0xffff << L2_DC_SIZE_SHFT)
 71  #define  L2_DC_ASSOC_SHFT		12
 72  #define  L2_DC_ASSOC_MASK		(0xf << L2_DC_ASSOC_SHFT)
 73  #define  L2_DC_LINE_TAG_SHFT		8
 74  #define  L2_DC_LINE_TAG_MASK		(0xf << L2_DC_LINE_TAG_SHFT)
 75  #define  L2_DC_LINE_SIZE_SHFT		0
 76  #define  L2_DC_LINE_SIZE_MASK		(0xff << L2_DC_LINE_SIZE_SHFT)
 77  /* Fn0x80000006_EDX */
 78  #define  L3_DC_SIZE_SHFT		18
 79  #define  L3_DC_SIZE_MASK		(0x3fff << L3_DC_SIZE_SHFT)
 80  #define  L3_DC_ASSOC_SHFT		12
 81  #define  L3_DC_ASSOC_MASK		(0xf << L3_DC_ASSOC_SHFT)
 82  #define  L3_DC_LINE_TAG_SHFT		8
 83  #define  L3_DC_LINE_TAG_MASK		(0xf << L3_DC_LINE_TAG_SHFT)
 84  #define  L3_DC_LINE_SIZE_SHFT		0
 85  #define  L3_DC_LINE_SIZE_MASK		(0xff << L3_DC_LINE_SIZE_SHFT)
 86  
 87  #define CPUID_EXT_PM			0x80000007
 88  #define CPUID_MODEL			1
 89  
 90  #define CPUID_TLB_L1L2_1G_IDS		0x80000019
 91  /* Fn0x80000019_EAX */
 92  #define  L1_DAT_TLB_1G_ASSOC_SHFT	28
 93  #define  L1_DAT_TLB_1G_ASSOC_MASK	(0xf << L1_DAT_TLB_1G_ASSOC_SHFT)
 94  #define  L1_DAT_TLB_1G_SIZE_SHFT	16
 95  #define  L1_DAT_TLB_1G_SIZE_MASK	(0xfff << L1_DAT_TLB_1G_SIZE_SHFT)
 96  #define  L1_INST_TLB_1G_ASSOC_SHFT	12
 97  #define  L1_INST_TLB_1G_ASSOC_MASK	(0xf << L1_INST_TLB_1G_ASSOC_SHFT)
 98  #define  L1_INST_TLB_1G_SIZE_SHFT	0
 99  #define  L1_INST_TLB_1G_SIZE_MASK	(0xfff << L1_INST_TLB_1G_SIZE_SHFT)
100  /* Fn0x80000019_EBX */
101  #define  L2_DAT_TLB_1G_ASSOC_SHFT	28
102  #define  L2_DAT_TLB_1G_ASSOC_MASK	(0xf << L2_DAT_TLB_1G_ASSOC_SHFT)
103  #define  L2_DAT_TLB_1G_SIZE_SHFT	16
104  #define  L2_DAT_TLB_1G_SIZE_MASK	(0xfff << L2_DAT_TLB_1G_SIZE_SHFT)
105  #define  L2_INST_TLB_1G_ASSOC_SHFT	12
106  #define  L2_INST_TLB_1G_ASSOC_MASK	(0xf << L2_INST_TLB_1G_ASSOC_SHFT)
107  #define  L2_INST_TLB_1G_SIZE_SHFT	0
108  #define  L2_INST_TLB_1G_SIZE_MASK	(0xfff << L2_INST_TLB_1G_SIZE_SHFT)
109  
110  #define CPUID_CACHE_PROPS		0x8000001D
111  #define  CACHE_PROPS_0			0
112  #define  CACHE_PROPS_1			1
113  #define  CACHE_PROPS_2			2
114  #define  CACHE_PROPS_3			3
115  #define  NUM_SHARE_CACHE_SHFT		14
116  #define  NUM_SHARE_CACHE_MASK		(0xfff << NUM_SHARE_CACHE_SHFT)
117  #define  CACHE_INCLUSIVE_SHFT		1
118  #define  CACHE_INCLUSIVE_MASK		(0x1 << CACHE_INCLUSIVE_SHFT)
119  
120  #define CPUID_EBX_CORE_ID		0x8000001E
121  #define  CPUID_EBX_THREADS_SHIFT	8
122  #define  CPUID_EBX_THREADS_MASK		(0xff << CPUID_EBX_THREADS_SHIFT)
123  
124  #define CPUID_EBX_MEM_ENCRYPT		0x8000001f
125  #define  CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT	6
126  #define  CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK	(0x3f << CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT)
127  
128  #endif /* CPU_AMD_CPUID_H */