1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #ifndef CPU_X86_PAE_H
 4  #define CPU_X86_PAE_H
 5  
 6  #include <stdint.h>
 7  #include <stddef.h>
 8  
 9  /* Enable paging with cr3 value for page directory pointer table as well as PAE
10     option in cr4. */
11  void paging_enable_pae_cr3(uintptr_t cr3);
12  /* Enable paging as well as PAE option in cr4. */
13  void paging_enable_pae(void);
14  /* Disable paging as well as PAE option in cr4. */
15  void paging_disable_pae(void);
16  
17  /* Set/Clear NXE bit in IA32_EFER MSR */
18  void paging_set_nxe(int enable);
19  
20  #define PAT_UC		0
21  #define PAT_WC		1
22  #define PAT_WT		4
23  #define PAT_WP		5
24  #define PAT_WB		6
25  #define PAT_UC_MINUS	7
26  #define PAT_ENCODE(type, idx) (((uint64_t)PAT_ ## type) << 8*(idx))
27  
28  /* Set PAT MSR */
29  void paging_set_pat(uint64_t pat);
30  /* Set coreboot default PAT value. */
31  void paging_set_default_pat(void);
32  
33  /* Load page directory pointer table and page tables from cbfs identified by
34   * the provided the names then enable paging. Return 0 on success, < 0 on
35   * failure. */
36  int paging_enable_for_car(const char *pdpt_name, const char *pt_name);
37  
38  /* To be used with memset_pae and pae_map_2M_page */
39  #define PAE_VMEM_ALIGN (2 * MiB)
40  #define PAE_VMEM_SIZE (2 * MiB)
41  #define PAE_PGTL_ALIGN (4 * KiB)
42  #define PAE_PGTL_SIZE (20 * KiB)
43  
44  int init_pae_pagetables(void *pgtbl);
45  
46  void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr);
47  
48  int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
49  	       void *vmem_addr);
50  
51  #endif /* CPU_X86_PAE_H  */