mc146818rtc.h
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef PC80_MC146818RTC_H 4 #define PC80_MC146818RTC_H 5 6 #include <arch/io.h> 7 #include <types.h> 8 9 #define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0) 10 #define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1) 11 12 #define RTC_PORT_BANK0(x) (RTC_BASE_PORT_BANK0 + (x)) 13 14 /* control registers - Moto names 15 */ 16 #define RTC_REG_A 10 17 #define RTC_REG_B 11 18 #define RTC_REG_C 12 19 #define RTC_REG_D 13 20 21 /********************************************************************** 22 * register details 23 **********************************************************************/ 24 #define RTC_FREQ_SELECT RTC_REG_A 25 26 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 27 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 28 * totaling to a max high interval of 2.228 ms. 29 */ 30 # define RTC_UIP 0x80 31 # define RTC_DIV_CTL 0x70 32 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 33 # define RTC_REF_CLCK_4MHZ 0x00 34 # define RTC_REF_CLCK_1MHZ 0x10 35 # define RTC_REF_CLCK_32KHZ 0x20 36 /* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */ 37 # define RTC_AMD_BANK_SELECT 0x10 38 /* 2 values for divider stage reset, others for "testing purposes only" */ 39 # define RTC_DIV_RESET1 0x60 40 # define RTC_DIV_RESET2 0x70 41 /* Periodic intr. / Square wave rate select. 0 = none, 42 * 1 = 32.8kHz,... 15 = 2Hz 43 */ 44 # define RTC_RATE_SELECT 0x0F 45 # define RTC_RATE_NONE 0x00 46 # define RTC_RATE_32786HZ 0x01 47 # define RTC_RATE_16384HZ 0x02 48 # define RTC_RATE_8192HZ 0x03 49 # define RTC_RATE_4096HZ 0x04 50 # define RTC_RATE_2048HZ 0x05 51 # define RTC_RATE_1024HZ 0x06 52 # define RTC_RATE_512HZ 0x07 53 # define RTC_RATE_256HZ 0x08 54 # define RTC_RATE_128HZ 0x09 55 # define RTC_RATE_64HZ 0x0a 56 # define RTC_RATE_32HZ 0x0b 57 # define RTC_RATE_16HZ 0x0c 58 # define RTC_RATE_8HZ 0x0d 59 # define RTC_RATE_4HZ 0x0e 60 # define RTC_RATE_2HZ 0x0f 61 62 /**********************************************************************/ 63 #define RTC_CONTROL RTC_REG_B 64 # define RTC_SET 0x80 /* disable updates for clock setting */ 65 # define RTC_PIE 0x40 /* periodic interrupt enable */ 66 # define RTC_AIE 0x20 /* alarm interrupt enable */ 67 # define RTC_UIE 0x10 /* update-finished interrupt enable */ 68 # define RTC_SQWE 0x08 /* enable square-wave output */ 69 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 70 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 71 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 72 73 /**********************************************************************/ 74 #define RTC_INTR_FLAGS RTC_REG_C 75 /* caution - cleared by read */ 76 # define RTC_IRQF 0x80 /* any of the following 3 is active */ 77 # define RTC_PF 0x40 78 # define RTC_AF 0x20 79 # define RTC_UF 0x10 80 81 /**********************************************************************/ 82 #define RTC_VALID RTC_REG_D 83 # define RTC_VRT 0x80 /* valid RAM and time */ 84 /**********************************************************************/ 85 86 /* Date and Time in RTC CMOS */ 87 #define RTC_CLK_SECOND 0 88 #define RTC_CLK_SECOND_ALARM 1 89 #define RTC_CLK_MINUTE 2 90 #define RTC_CLK_MINUTE_ALARM 3 91 #define RTC_CLK_HOUR 4 92 #define RTC_CLK_HOUR_ALARM 5 93 #define RTC_CLK_DAYOFWEEK 6 94 #define RTC_CLK_DAYOFMONTH 7 95 #define RTC_CLK_MONTH 8 96 #define RTC_CLK_YEAR 9 97 #define RTC_CLK_ALTCENTURY 0x32 98 99 #define RTC_DATE_ALARM RTC_REG_D 100 #define RTC_MONTH_ALARM 0 101 102 /* On PCs, the checksum is built only over bytes 16..45 */ 103 #define PC_CKS_RANGE_START 16 104 #define PC_CKS_RANGE_END 45 105 #define PC_CKS_LOC 46 106 107 /* Tracking of fallback/normal boot. */ 108 #define RTC_BOOT_BYTE 48 109 #define RTC_BOOT_NORMAL 0x1 110 111 static inline unsigned char cmos_read(unsigned char addr) 112 { 113 int port = RTC_BASE_PORT_BANK0; 114 if (addr >= 128) { 115 port = RTC_BASE_PORT_BANK1; 116 addr -= 128; 117 } 118 outb(addr, port + 0); 119 return inb(port + 1); 120 } 121 122 static inline void cmos_write_inner(unsigned char val, unsigned char addr) 123 { 124 int port = RTC_BASE_PORT_BANK0; 125 if (addr >= 128) { 126 port = RTC_BASE_PORT_BANK1; 127 addr -= 128; 128 } 129 outb(addr, port + 0); 130 outb(val, port + 1); 131 } 132 133 static inline u8 cmos_disable_rtc(void) 134 { 135 u8 control_state = cmos_read(RTC_CONTROL); 136 if (!(control_state & RTC_SET)) 137 cmos_write_inner(control_state | RTC_SET, RTC_CONTROL); 138 return control_state; 139 } 140 141 static inline void cmos_restore_rtc(u8 control_state) 142 { 143 if (!(control_state & RTC_SET)) 144 cmos_write_inner(control_state, RTC_CONTROL); 145 } 146 147 static inline void cmos_write(unsigned char val, unsigned char addr) 148 { 149 u8 control_state; 150 151 /* 152 * There are various places where RTC bits might be hiding, 153 * eg. the Century / AltCentury byte. So to be safe, disable 154 * RTC before changing any value. 155 */ 156 if (addr != RTC_CONTROL) 157 control_state = cmos_disable_rtc(); 158 cmos_write_inner(val, addr); 159 if (addr != RTC_CONTROL) 160 cmos_restore_rtc(control_state); 161 } 162 163 static inline u32 cmos_read32(u8 offset) 164 { 165 u32 value = 0; 166 u8 i; 167 for (i = 0; i < sizeof(value); ++i) 168 value |= cmos_read(offset + i) << (i << 3); 169 return value; 170 } 171 172 static inline void cmos_write32(u32 value, u8 offset) 173 { 174 u8 i; 175 for (i = 0; i < sizeof(value); ++i) 176 cmos_write((value >> (i << 3)) & 0xff, offset + i); 177 } 178 179 void cmos_init(bool invalid); 180 void cmos_check_update_date(void); 181 int cmos_error(void); 182 int cmos_lb_cks_valid(void); 183 184 int cmos_checksum_valid(int range_start, int range_end, int cks_loc); 185 void cmos_set_checksum(int range_start, int range_end, int cks_loc); 186 187 #endif /* PC80_MC146818RTC_H */