smbios.h
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SMBIOS_H 4 #define SMBIOS_H 5 6 #include <types.h> 7 #include <memory_info.h> 8 9 #define update_max(len, max_len, stmt) \ 10 do { \ 11 int tmp = stmt; \ 12 \ 13 max_len = MAX(max_len, tmp); \ 14 len += tmp; \ 15 } while (0) 16 17 unsigned long smbios_write_tables(unsigned long start); 18 int smbios_add_string(u8 *start, const char *str); 19 int smbios_string_table_len(u8 *start); 20 21 struct smbios_header; 22 int smbios_full_table_len(struct smbios_header *header, u8 *str_table_start); 23 void *smbios_carve_table(unsigned long start, u8 type, u8 length, u16 handle); 24 25 /* Used by mainboard to add an on-board device */ 26 enum misc_slot_type; 27 enum misc_slot_length; 28 enum misc_slot_usage; 29 enum slot_data_bus_bandwidth; 30 int smbios_write_type9(unsigned long *current, int *handle, 31 const char *name, const enum misc_slot_type type, 32 const enum slot_data_bus_bandwidth bandwidth, 33 const enum misc_slot_usage usage, 34 const enum misc_slot_length length, 35 const u16 id, u8 slot_char1, u8 slot_char2, 36 u8 segment_group, u8 bus, u8 dev_func); 37 enum smbios_bmc_interface_type; 38 int smbios_write_type38(unsigned long *current, int *handle, 39 const enum smbios_bmc_interface_type interface_type, 40 const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr, 41 const u64 base_addr, const u8 base_modifier, 42 const u8 irq); 43 int smbios_write_type41(unsigned long *current, int *handle, 44 const char *name, u8 instance, u16 segment_group, 45 u8 bus, u8 device, u8 function, u8 device_type); 46 enum smbios_temp_location; 47 enum smbios_temp_status; 48 int smbios_write_type28(unsigned long *current, int *handle, 49 const char *name, 50 const enum smbios_temp_location location, 51 const enum smbios_temp_status status, 52 u16 max_value, u16 min_value, 53 u16 resolution, u16 tolerance, 54 u16 accuracy, 55 u32 oem, 56 u16 nominal_value); 57 58 int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, 59 const u8 major_spec_ver, const u8 minor_spec_ver, 60 const u32 fw_ver1, const u32 fw_ver2, const char *description, 61 const u64 characteristics, const u32 oem_defined); 62 63 struct device; 64 int get_smbios_data(struct device *dev, int *handle, unsigned long *current); 65 66 const char *smbios_system_manufacturer(void); 67 const char *smbios_system_product_name(void); 68 const char *smbios_system_serial_number(void); 69 const char *smbios_system_version(void); 70 void smbios_system_set_uuid(u8 *uuid); 71 const char *smbios_system_sku(void); 72 73 void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count); 74 unsigned int smbios_cpu_get_max_speed_mhz(void); 75 unsigned int smbios_cpu_get_current_speed_mhz(void); 76 unsigned int smbios_cpu_get_voltage(void); 77 unsigned int smbios_get_max_sockets(void); 78 unsigned int smbios_soc_get_max_sockets(void); 79 80 const char *smbios_mainboard_manufacturer(void); 81 const char *smbios_mainboard_product_name(void); 82 const char *smbios_mainboard_serial_number(void); 83 const char *smbios_mainboard_version(void); 84 85 const char *smbios_mainboard_bios_version(void); 86 const char *smbios_mainboard_asset_tag(void); 87 u8 smbios_mainboard_feature_flags(void); 88 const char *smbios_mainboard_location_in_chassis(void); 89 const char *smbios_chassis_version(void); 90 const char *smbios_chassis_serial_number(void); 91 const char *smbios_processor_serial_number(void); 92 u8 smbios_chassis_power_cords(void); 93 94 /* This string could be filled late in payload. */ 95 void smbios_type0_bios_version(uintptr_t address); 96 97 void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); 98 99 unsigned int smbios_processor_external_clock(void); 100 unsigned int smbios_processor_characteristics(void); 101 struct cpuid_result; 102 unsigned int smbios_processor_family(struct cpuid_result res); 103 104 unsigned int smbios_cache_error_correction_type(u8 level); 105 unsigned int smbios_cache_sram_type(void); 106 unsigned int smbios_cache_conf_operation_mode(u8 level); 107 108 /* Used by mainboard to add port information of type 8 */ 109 struct port_information; 110 int smbios_write_type8(unsigned long *current, int *handle, 111 const struct port_information *port, 112 size_t num_ports); 113 114 #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) 115 #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) 116 #define BIOS_CHARACTERISTICS_PNP (1 << 9) 117 #define BIOS_CHARACTERISTICS_APM (1 << 10) 118 #define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) 119 #define BIOS_CHARACTERISTICS_SHADOW (1 << 12) 120 #define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) 121 #define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) 122 #define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) 123 124 #define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) 125 #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) 126 127 #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) 128 #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) 129 #define BIOS_MEMORY_ECC_SCRUBBING (1 << 5) 130 131 #define MEMORY_TYPE_DETAIL_OTHER (1 << 1) 132 #define MEMORY_TYPE_DETAIL_UNKNOWN (1 << 2) 133 #define MEMORY_TYPE_DETAIL_FAST_PAGED (1 << 3) 134 #define MEMORY_TYPE_DETAIL_STATIC_COLUMN (1 << 4) 135 #define MEMORY_TYPE_DETAIL_PSEUDO_STATIC (1 << 5) 136 #define MEMORY_TYPE_DETAIL_RAMBUS (1 << 6) 137 #define MEMORY_TYPE_DETAIL_SYNCHRONOUS (1 << 7) 138 #define MEMORY_TYPE_DETAIL_CMOS (1 << 8) 139 #define MEMORY_TYPE_DETAIL_EDO (1 << 9) 140 #define MEMORY_TYPE_DETAIL_WINDOW_DRAM (1 << 10) 141 #define MEMORY_TYPE_DETAIL_CACHE_DRAM (1 << 11) 142 #define MEMORY_TYPE_DETAIL_NON_VOLATILE (1 << 12) 143 #define MEMORY_TYPE_DETAIL_REGISTERED (1 << 13) 144 #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) 145 #define MEMORY_TYPE_DETAIL_LRDIMM (1 << 15) 146 147 #define MEMORY_TECHNOLOGY_OTHER 0x01 148 #define MEMORY_TECHNOLOGY_UNKNOWN 0x02 149 #define MEMORY_TECHNOLOGY_DRAM 0x03 150 #define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 151 #define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 152 #define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 153 #define MEMORY_TECHNOLOGY_INTEL_PERSISTENT 0x07 154 155 #define MEMORY_OPERATING_MODE_CAP_OTHER (1 << 1) 156 #define MEMORY_OPERATING_MODE_CAP_UNKNOWN (1 << 2) 157 #define MEMORY_OPERATING_MODE_CAP_VOLATILE (1 << 3) 158 #define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) 159 #define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) 160 161 typedef enum { 162 MEMORY_BUS_WIDTH_8 = 0, 163 MEMORY_BUS_WIDTH_16 = 1, 164 MEMORY_BUS_WIDTH_32 = 2, 165 MEMORY_BUS_WIDTH_64 = 3, 166 MEMORY_BUS_WIDTH_128 = 4, 167 MEMORY_BUS_WIDTH_256 = 5, 168 MEMORY_BUS_WIDTH_512 = 6, 169 MEMORY_BUS_WIDTH_1024 = 7, 170 MEMORY_BUS_WIDTH_MAX = 7, 171 } smbios_memory_bus_width; 172 173 typedef enum { 174 MEMORY_FORMFACTOR_OTHER = 0x01, 175 MEMORY_FORMFACTOR_UNKNOWN = 0x02, 176 MEMORY_FORMFACTOR_SIMM = 0x03, 177 MEMORY_FORMFACTOR_SIP = 0x04, 178 MEMORY_FORMFACTOR_CHIP = 0x05, 179 MEMORY_FORMFACTOR_DIP = 0x06, 180 MEMORY_FORMFACTOR_ZIP = 0x07, 181 MEMORY_FORMFACTOR_PROPRIETARY_CARD = 0x08, 182 MEMORY_FORMFACTOR_DIMM = 0x09, 183 MEMORY_FORMFACTOR_TSOP = 0x0a, 184 MEMORY_FORMFACTOR_ROC = 0x0b, 185 MEMORY_FORMFACTOR_RIMM = 0x0c, 186 MEMORY_FORMFACTOR_SODIMM = 0x0d, 187 MEMORY_FORMFACTOR_SRIMM = 0x0e, 188 MEMORY_FORMFACTOR_FBDIMM = 0x0f, 189 MEMORY_FORMFACTOR_DIE = 0x10, 190 } smbios_memory_form_factor; 191 192 typedef enum { 193 MEMORY_TYPE_OTHER = 0x01, 194 MEMORY_TYPE_UNKNOWN = 0x02, 195 MEMORY_TYPE_DRAM = 0x03, 196 MEMORY_TYPE_EDRAM = 0x04, 197 MEMORY_TYPE_VRAM = 0x05, 198 MEMORY_TYPE_SRAM = 0x06, 199 MEMORY_TYPE_RAM = 0x07, 200 MEMORY_TYPE_ROM = 0x08, 201 MEMORY_TYPE_FLASH = 0x09, 202 MEMORY_TYPE_EEPROM = 0x0a, 203 MEMORY_TYPE_FEPROM = 0x0b, 204 MEMORY_TYPE_EPROM = 0x0c, 205 MEMORY_TYPE_CDRAM = 0x0d, 206 MEMORY_TYPE_3DRAM = 0x0e, 207 MEMORY_TYPE_SDRAM = 0x0f, 208 MEMORY_TYPE_SGRAM = 0x10, 209 MEMORY_TYPE_RDRAM = 0x11, 210 MEMORY_TYPE_DDR = 0x12, 211 MEMORY_TYPE_DDR2 = 0x13, 212 MEMORY_TYPE_DDR2_FBDIMM = 0x14, 213 MEMORY_TYPE_DDR3 = 0x18, 214 MEMORY_TYPE_FBD2 = 0x19, 215 MEMORY_TYPE_DDR4 = 0x1a, 216 MEMORY_TYPE_LPDDR = 0x1b, 217 MEMORY_TYPE_LPDDR2 = 0x1c, 218 MEMORY_TYPE_LPDDR3 = 0x1d, 219 MEMORY_TYPE_LPDDR4 = 0x1e, 220 MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, 221 MEMORY_TYPE_HBM = 0x20, 222 MEMORY_TYPE_HBM2 = 0x21, 223 MEMORY_TYPE_DDR5 = 0x22, 224 MEMORY_TYPE_LPDDR5 = 0x23, 225 MEMORY_TYPE_HBM3 = 0x24, 226 } smbios_memory_type; 227 228 typedef enum { 229 MEMORY_ARRAY_LOCATION_OTHER = 0x01, 230 MEMORY_ARRAY_LOCATION_UNKNOWN = 0x02, 231 MEMORY_ARRAY_LOCATION_SYSTEM_BOARD = 0x03, 232 MEMORY_ARRAY_LOCATION_ISA_ADD_ON = 0x04, 233 MEMORY_ARRAY_LOCATION_EISA_ADD_ON = 0x05, 234 MEMORY_ARRAY_LOCATION_PCI_ADD_ON = 0x06, 235 MEMORY_ARRAY_LOCATION_MCA_ADD_ON = 0x07, 236 MEMORY_ARRAY_LOCATION_PCMCIA_ADD_ON = 0x08, 237 MEMORY_ARRAY_LOCATION_PROPRIETARY_ADD_ON = 0x09, 238 MEMORY_ARRAY_LOCATION_NUBUS = 0x0a, 239 MEMORY_ARRAY_LOCATION_PC_98_C20_ADD_ON = 0xa0, 240 MEMORY_ARRAY_LOCATION_PC_98_C24_ADD_ON = 0xa1, 241 MEMORY_ARRAY_LOCATION_PC_98_E_ADD_ON = 0xa2, 242 MEMORY_ARRAY_LOCATION_PC_98_LOCAL_BUS_ADD_ON = 0xa3, 243 MEMORY_ARRAY_LOCATION_CXL_FLEXBUS_1_0_ADD_ON = 0xa4, 244 } smbios_memory_array_location; 245 246 typedef enum { 247 MEMORY_ARRAY_USE_OTHER = 0x01, 248 MEMORY_ARRAY_USE_UNKNOWN = 0x02, 249 MEMORY_ARRAY_USE_SYSTEM = 0x03, 250 MEMORY_ARRAY_USE_VIDEO = 0x04, 251 MEMORY_ARRAY_USE_FLASH = 0x05, 252 MEMORY_ARRAY_USE_NVRAM = 0x06, 253 MEMORY_ARRAY_USE_CACHE = 0x07, 254 } smbios_memory_array_use; 255 256 typedef enum { 257 MEMORY_ARRAY_ECC_OTHER = 0x01, 258 MEMORY_ARRAY_ECC_UNKNOWN = 0x02, 259 MEMORY_ARRAY_ECC_NONE = 0x03, 260 MEMORY_ARRAY_ECC_PARITY = 0x04, 261 MEMORY_ARRAY_ECC_SINGLE_BIT = 0x05, 262 MEMORY_ARRAY_ECC_MULTI_BIT = 0x06, 263 MEMORY_ARRAY_ECC_CRC = 0x07, 264 } smbios_memory_array_ecc; 265 266 #define SMBIOS_STATE_SAFE 3 267 typedef enum { 268 SMBIOS_BIOS_INFORMATION = 0, 269 SMBIOS_SYSTEM_INFORMATION = 1, 270 SMBIOS_BOARD_INFORMATION = 2, 271 SMBIOS_SYSTEM_ENCLOSURE = 3, 272 SMBIOS_PROCESSOR_INFORMATION = 4, 273 SMBIOS_CACHE_INFORMATION = 7, 274 SMBIOS_PORT_CONNECTOR_INFORMATION = 8, 275 SMBIOS_SYSTEM_SLOTS = 9, 276 SMBIOS_OEM_STRINGS = 11, 277 SMBIOS_EVENT_LOG = 15, 278 SMBIOS_PHYS_MEMORY_ARRAY = 16, 279 SMBIOS_MEMORY_DEVICE = 17, 280 SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, 281 SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS = 20, 282 SMBIOS_TEMPERATURE_PROBE = 28, 283 SMBIOS_SYSTEM_BOOT_INFORMATION = 32, 284 SMBIOS_IPMI_DEVICE_INFORMATION = 38, 285 SMBIOS_SYSTEM_POWER_SUPPLY = 39, 286 SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, 287 SMBIOS_TPM_DEVICE = 43, 288 SMBIOS_END_OF_TABLE = 127, 289 } smbios_struct_type_t; 290 291 struct smbios_entry { 292 u8 anchor[4]; 293 u8 checksum; 294 u8 length; 295 u8 major_version; 296 u8 minor_version; 297 u16 max_struct_size; 298 u8 entry_point_rev; 299 u8 formwatted_area[5]; 300 u8 intermediate_anchor_string[5]; 301 u8 intermediate_checksum; 302 u16 struct_table_length; 303 u32 struct_table_address; 304 u16 struct_count; 305 u8 smbios_bcd_revision; 306 } __packed; 307 308 struct smbios_entry30 { 309 u8 anchor[5]; 310 u8 checksum; 311 u8 length; 312 u8 major_version; 313 u8 minor_version; 314 u8 smbios_doc_rev; 315 u8 entry_point_rev; 316 u8 reserved; 317 u32 struct_table_length; 318 u64 struct_table_address; 319 } __packed; 320 321 struct smbios_header { 322 u8 type; 323 u8 length; 324 u16 handle; 325 } __packed; 326 327 struct smbios_type0 { 328 struct smbios_header header; 329 u8 vendor; 330 u8 bios_version; 331 u16 bios_start_segment; 332 u8 bios_release_date; 333 u8 bios_rom_size; 334 u64 bios_characteristics; 335 u8 bios_characteristics_ext1; 336 u8 bios_characteristics_ext2; 337 u8 system_bios_major_release; 338 u8 system_bios_minor_release; 339 u8 ec_major_release; 340 u8 ec_minor_release; 341 u16 extended_bios_rom_size; 342 u8 eos[2]; 343 } __packed; 344 345 typedef enum { 346 SMBIOS_WAKEUP_TYPE_RESERVED = 0x00, 347 SMBIOS_WAKEUP_TYPE_OTHER = 0x01, 348 SMBIOS_WAKEUP_TYPE_UNKNOWN = 0x02, 349 SMBIOS_WAKEUP_TYPE_APM_TIMER = 0x03, 350 SMBIOS_WAKEUP_TYPE_MODEM_RING = 0x04, 351 SMBIOS_WAKEUP_TYPE_LAN_REMOTE = 0x05, 352 SMBIOS_WAKEUP_TYPE_POWER_SWITCH = 0x06, 353 SMBIOS_WAKEUP_TYPE_PCI_PME = 0x07, 354 SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED = 0x08, 355 } smbios_wakeup_type; 356 357 struct smbios_type1 { 358 struct smbios_header header; 359 u8 manufacturer; 360 u8 product_name; 361 u8 version; 362 u8 serial_number; 363 u8 uuid[16]; 364 u8 wakeup_type; 365 u8 sku; 366 u8 family; 367 u8 eos[2]; 368 } __packed; 369 370 #define SMBIOS_FEATURE_FLAGS_HOSTING_BOARD (1 << 0) 371 #define SMBIOS_FEATURE_FLAGS_REQUIRES_DAUGHTER_CARD (1 << 1) 372 #define SMBIOS_FEATURE_FLAGS_REMOVABLE (1 << 2) 373 #define SMBIOS_FEATURE_FLAGS_REPLACEABLE (1 << 3) 374 #define SMBIOS_FEATURE_FLAGS_HOT_SWAPPABLE (1 << 4) 375 376 typedef enum { 377 SMBIOS_BOARD_TYPE_UNKNOWN = 0x01, 378 SMBIOS_BOARD_TYPE_OTHER = 0x02, 379 SMBIOS_BOARD_TYPE_SERVER_BLADE = 0x03, 380 SMBIOS_BOARD_TYPE_CONNECTIVITY_SWITCH = 0x04, 381 SMBIOS_BOARD_TYPE_SYSTEM_MANAGEMENT_MODULE = 0x05, 382 SMBIOS_BOARD_TYPE_PROCESSOR_MODULE = 0x06, 383 SMBIOS_BOARD_TYPE_IO_MODULE = 0x07, 384 SMBIOS_BOARD_TYPE_MEMORY_MODULE = 0x08, 385 SMBIOS_BOARD_TYPE_DAUGHTER_BOARD = 0x09, 386 SMBIOS_BOARD_TYPE_MOTHERBOARD = 0x0a, 387 SMBIOS_BOARD_TYPE_PROCESSOR_MEMORY_MODULE = 0x0b, 388 SMBIOS_BOARD_TYPE_PROCESSOR_IO_MODULE = 0x0c, 389 SMBIOS_BOARD_TYPE_INTERCONNECT_BOARD = 0x0d, 390 } smbios_board_type; 391 392 struct smbios_type2 { 393 struct smbios_header header; 394 u8 manufacturer; 395 u8 product_name; 396 u8 version; 397 u8 serial_number; 398 u8 asset_tag; 399 u8 feature_flags; 400 u8 location_in_chassis; 401 u16 chassis_handle; 402 u8 board_type; 403 u8 eos[2]; 404 } __packed; 405 406 typedef enum { 407 SMBIOS_ENCLOSURE_OTHER = 0x01, 408 SMBIOS_ENCLOSURE_UNKNOWN = 0x02, 409 SMBIOS_ENCLOSURE_DESKTOP = 0x03, 410 SMBIOS_ENCLOSURE_LOW_PROFILE_DESKTOP = 0x04, 411 SMBIOS_ENCLOSURE_PIZZA_BOX = 0x05, 412 SMBIOS_ENCLOSURE_MINI_TOWER = 0x06, 413 SMBIOS_ENCLOSURE_TOWER = 0x07, 414 SMBIOS_ENCLOSURE_PORTABLE = 0x08, 415 SMBIOS_ENCLOSURE_LAPTOP = 0x09, 416 SMBIOS_ENCLOSURE_NOTEBOOK = 0x0a, 417 SMBIOS_ENCLOSURE_HAND_HELD = 0x0b, 418 SMBIOS_ENCLOSURE_DOCKING_STATION = 0x0c, 419 SMBIOS_ENCLOSURE_ALL_IN_ONE = 0x0d, 420 SMBIOS_ENCLOSURE_SUB_NOTEBOOK = 0x0e, 421 SMBIOS_ENCLOSURE_SPACE_SAVING = 0x0f, 422 SMBIOS_ENCLOSURE_LUNCH_BOX = 0x10, 423 SMBIOS_ENCLOSURE_MAIN_SERVER_CHASSIS = 0x11, 424 SMBIOS_ENCLOSURE_EXPANSION_CHASSIS = 0x12, 425 SMBIOS_ENCLOSURE_SUBCHASSIS = 0x13, 426 SMBIOS_ENCLOSURE_BUS_EXPANSION_CHASSIS = 0x14, 427 SMBIOS_ENCLOSURE_PERIPHERAL_CHASSIS = 0x15, 428 SMBIOS_ENCLOSURE_RAID_CHASSIS = 0x16, 429 SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS = 0x17, 430 SMBIOS_ENCLOSURE_SEALED_CASE_PC = 0x18, 431 SMBIOS_ENCLOSURE_MULTI_SYSTEM_CHASSIS = 0x19, 432 SMBIOS_ENCLOSURE_COMPACT_PCI = 0x1a, 433 SMBIOS_ENCLOSURE_ADVANCED_TCA = 0x1b, 434 SMBIOS_ENCLOSURE_BLADE = 0x1c, 435 SMBIOS_ENCLOSURE_BLADE_ENCLOSURE = 0x1d, 436 SMBIOS_ENCLOSURE_TABLET = 0x1e, 437 SMBIOS_ENCLOSURE_CONVERTIBLE = 0x1f, 438 SMBIOS_ENCLOSURE_DETACHABLE = 0x20, 439 SMBIOS_ENCLOSURE_IOT_GATEWAY = 0x21, 440 SMBIOS_ENCLOSURE_EMBEDDED_PC = 0x22, 441 SMBIOS_ENCLOSURE_MINI_PC = 0x23, 442 SMBIOS_ENCLOSURE_STICK_PC = 0x24, 443 } smbios_enclosure_type; 444 445 struct smbios_type3 { 446 struct smbios_header header; 447 u8 manufacturer; 448 u8 _type; 449 u8 version; 450 u8 serial_number; 451 u8 asset_tag_number; 452 u8 bootup_state; 453 u8 power_supply_state; 454 u8 thermal_state; 455 u8 security_status; 456 u32 oem_defined; 457 u8 height; 458 u8 number_of_power_cords; 459 u8 element_count; 460 u8 element_record_length; 461 u8 sku_number; 462 u8 eos[2]; 463 } __packed; 464 465 struct smbios_type4 { 466 struct smbios_header header; 467 u8 socket_designation; 468 u8 processor_type; 469 u8 processor_family; 470 u8 processor_manufacturer; 471 u32 processor_id[2]; 472 u8 processor_version; 473 u8 voltage; 474 u16 external_clock; 475 u16 max_speed; 476 u16 current_speed; 477 u8 status; 478 u8 processor_upgrade; 479 u16 l1_cache_handle; 480 u16 l2_cache_handle; 481 u16 l3_cache_handle; 482 u8 serial_number; 483 u8 asset_tag; 484 u8 part_number; 485 u8 core_count; 486 u8 core_enabled; 487 u8 thread_count; 488 u16 processor_characteristics; 489 u16 processor_family2; 490 u16 core_count2; 491 u16 core_enabled2; 492 u16 thread_count2; 493 u8 eos[2]; 494 } __packed; 495 496 /* defines for smbios_type4 */ 497 498 #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) 499 #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) 500 501 enum smbios_processor_type { 502 SMBIOS_PROCESSOR_TYPE_OTHER = 0x01, 503 SMBIOS_PROCESSOR_TYPE_UNKNOWN = 0x02, 504 SMBIOS_PROCESSOR_TYPE_CENTRAL = 0x03, 505 SMBIOS_PROCESSOR_TYPE_MATH = 0x04, 506 SMBIOS_PROCESSOR_TYPE_DSP = 0x05, 507 SMBIOS_PROCESSOR_TYPE_VIDEO = 0x06, 508 }; 509 510 /* enum for socket type */ 511 enum smbios_processor_upgrade_field { 512 PROCESSOR_UPGRADE_OTHER = 0x01, 513 PROCESSOR_UPGRADE_UNKNOWN = 0x02, 514 PROCESSOR_UPGRADE_DAUGHTER_BOARD = 0x03, 515 PROCESSOR_UPGRADE_ZIF_SOCKET = 0x04, 516 PROCESSOR_UPGRADE_REPLACEABLE_PIGGY_BACK = 0x05, 517 PROCESSOR_UPGRADE_NONE = 0x06, 518 PROCESSOR_UPGRADE_LIF_SOCKET = 0x07, 519 PROCESSOR_UPGRADE_SLOT_1 = 0x08, 520 PROCESSOR_UPGRADE_SLOT_2 = 0x09, 521 PROCESSOR_UPGRADE_370_PIN_SOCKET = 0x0a, 522 PROCESSOR_UPGRADE_SLOT_A = 0x0b, 523 PROCESSOR_UPGRADE_SLOT_M = 0x0c, 524 PROCESSOR_UPGRADE_SOCKET_423 = 0x0d, 525 PROCESSOR_UPGRADE_SOCKET_A = 0x0e, 526 PROCESSOR_UPGRADE_SOCKET_478 = 0x0f, 527 PROCESSOR_UPGRADE_SOCKET_754 = 0x10, 528 PROCESSOR_UPGRADE_SOCKET_940 = 0x11, 529 PROCESSOR_UPGRADE_SOCKET_939 = 0x12, 530 PROCESSOR_UPGRADE_SOCKET_MPGA604 = 0x13, 531 PROCESSOR_UPGRADE_SOCKET_LGA771 = 0x14, 532 PROCESSOR_UPGRADE_SOCKET_LGA775 = 0x15, 533 PROCESSOR_UPGRADE_SOCKET_S1 = 0x16, 534 PROCESSOR_UPGRADE_SOCKET_AM2 = 0x17, 535 PROCESSOR_UPGRADE_SOCKET_F = 0x18, 536 PROCESSOR_UPGRADE_SOCKET_LGA1366 = 0x19, 537 PROCESSOR_UPGRADE_SOCKET_G34 = 0x1a, 538 PROCESSOR_UPGRADE_SOCKET_AM3 = 0x1b, 539 PROCESSOR_UPGRADE_SOCKET_C32 = 0x1c, 540 PROCESSOR_UPGRADE_SOCKET_LGA1156 = 0x1d, 541 PROCESSOR_UPGRADE_SOCKET_LGA1567 = 0x1e, 542 PROCESSOR_UPGRADE_SOCKET_PGA988A = 0x1f, 543 PROCESSOR_UPGRADE_SOCKET_BGA1288 = 0x20, 544 PROCESSOR_UPGRADE_SOCKET_RPGA988B = 0x21, 545 PROCESSOR_UPGRADE_SOCKET_BGA1023 = 0x22, 546 PROCESSOR_UPGRADE_SOCKET_BGA1224 = 0x23, 547 PROCESSOR_UPGRADE_SOCKET_LGA1155 = 0x24, 548 PROCESSOR_UPGRADE_SOCKET_LGA1356 = 0x25, 549 PROCESSOR_UPGRADE_SOCKET_LGA2011 = 0x26, 550 PROCESSOR_UPGRADE_SOCKET_FS1 = 0x27, 551 PROCESSOR_UPGRADE_SOCKET_FS2 = 0x28, 552 PROCESSOR_UPGRADE_SOCKET_FM1 = 0x29, 553 PROCESSOR_UPGRADE_SOCKET_FM2 = 0x2a, 554 PROCESSOR_UPGRADE_SOCKET_LGA2011_3 = 0x2b, 555 PROCESSOR_UPGRADE_SOCKET_LGA1356_3 = 0x2c, 556 PROCESSOR_UPGRADE_SOCKET_LGA1150 = 0x2d, 557 PROCESSOR_UPGRADE_SOCKET_BGA1168 = 0x2e, 558 PROCESSOR_UPGRADE_SOCKET_BGA1234 = 0x2f, 559 PROCESSOR_UPGRADE_SOCKET_BGA1364 = 0x30, 560 PROCESSOR_UPGRADE_SOCKET_AM4 = 0x31, 561 PROCESSOR_UPGRADE_SOCKET_LGA1151 = 0x32, 562 PROCESSOR_UPGRADE_SOCKET_BGA1356 = 0x33, 563 PROCESSOR_UPGRADE_SOCKET_BGA1440 = 0x34, 564 PROCESSOR_UPGRADE_SOCKET_BGA1515 = 0x35, 565 PROCESSOR_UPGRADE_SOCKET_LGA3647_1 = 0x36, 566 PROCESSOR_UPGRADE_SOCKET_SP3 = 0x37, 567 PROCESSOR_UPGRADE_SOCKET_SP3R2 = 0x38, 568 PROCESSOR_UPGRADE_SOCKET_LGA2066 = 0x39, 569 PROCESSOR_UPGRADE_SOCKET_BGA1392 = 0x3a, 570 PROCESSOR_UPGRADE_SOCKET_BGA1510 = 0x3b, 571 PROCESSOR_UPGRADE_SOCKET_BGA1528 = 0x3c, 572 PROCESSOR_UPGRADE_SOCKET_LGA4189 = 0x3d, 573 PROCESSOR_UPGRADE_SOCKET_LGA1200 = 0x3e, 574 PROCESSOR_UPGRADE_SOCKET_LGA4677 = 0x3f, 575 PROCESSOR_UPGRADE_SOCKET_LGA1700 = 0x40, 576 PROCESSOR_UPGRADE_SOCKET_BGA1744 = 0x41, 577 PROCESSOR_UPGRADE_SOCKET_BGA1781 = 0x42, 578 PROCESSOR_UPGRADE_SOCKET_BGA1211 = 0x43, 579 PROCESSOR_UPGRADE_SOCKET_BGA2422 = 0x44, 580 PROCESSOR_UPGRADE_SOCKET_LGA1211 = 0x45, 581 PROCESSOR_UPGRADE_SOCKET_LGA2422 = 0x46, 582 PROCESSOR_UPGRADE_SOCKET_LGA5773 = 0x47, 583 PROCESSOR_UPGRADE_SOCKET_BGA5773 = 0x48, 584 }; 585 586 /* defines for processor family */ 587 #define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 588 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 589 #define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06 590 #define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c 591 #define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3 592 #define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe 593 594 /* defines for processor family 2 */ 595 #define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101 596 597 /* defines for processor characteristics */ 598 #define PROCESSOR_64BIT_CAPABLE (1 << 2) 599 #define PROCESSOR_MULTI_CORE (1 << 3) 600 #define PROCESSOR_POWER_PERFORMANCE_CONTROL (1 << 7) 601 602 /* defines for supported_sram_type/current_sram_type */ 603 604 #define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) 605 #define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN (1 << 1) 606 #define SMBIOS_CACHE_SRAM_TYPE_NON_BURST (1 << 2) 607 #define SMBIOS_CACHE_SRAM_TYPE_BURST (1 << 3) 608 #define SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST (1 << 4) 609 #define SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS (1 << 5) 610 #define SMBIOS_CACHE_SRAM_TYPE_ASYNCHRONOUS (1 << 6) 611 612 /* enum for error_correction_type */ 613 614 enum smbios_cache_error_corr { 615 SMBIOS_CACHE_ERROR_CORRECTION_OTHER = 1, 616 SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN, 617 SMBIOS_CACHE_ERROR_CORRECTION_NONE, 618 SMBIOS_CACHE_ERROR_CORRECTION_PARITY, 619 SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT, 620 SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT, 621 }; 622 623 /* enum for system_cache_type */ 624 625 enum smbios_cache_type { 626 SMBIOS_CACHE_TYPE_OTHER = 1, 627 SMBIOS_CACHE_TYPE_UNKNOWN, 628 SMBIOS_CACHE_TYPE_INSTRUCTION, 629 SMBIOS_CACHE_TYPE_DATA, 630 SMBIOS_CACHE_TYPE_UNIFIED, 631 }; 632 633 /* enum for associativity */ 634 635 enum smbios_cache_associativity { 636 SMBIOS_CACHE_ASSOCIATIVITY_OTHER = 1, 637 SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN, 638 SMBIOS_CACHE_ASSOCIATIVITY_DIRECT, 639 SMBIOS_CACHE_ASSOCIATIVITY_2WAY, 640 SMBIOS_CACHE_ASSOCIATIVITY_4WAY, 641 SMBIOS_CACHE_ASSOCIATIVITY_FULL, 642 SMBIOS_CACHE_ASSOCIATIVITY_8WAY, 643 SMBIOS_CACHE_ASSOCIATIVITY_16WAY, 644 SMBIOS_CACHE_ASSOCIATIVITY_12WAY, 645 SMBIOS_CACHE_ASSOCIATIVITY_24WAY, 646 SMBIOS_CACHE_ASSOCIATIVITY_32WAY, 647 SMBIOS_CACHE_ASSOCIATIVITY_48WAY, 648 SMBIOS_CACHE_ASSOCIATIVITY_64WAY, 649 SMBIOS_CACHE_ASSOCIATIVITY_20WAY, 650 }; 651 652 /* defines for cache_configuration */ 653 654 #define SMBIOS_CACHE_CONF_LEVEL(x) ((((x) - 1) & 0x7) << 0) 655 #define SMBIOS_CACHE_CONF_LOCATION(x) (((x) & 0x3) << 5) 656 #define SMBIOS_CACHE_CONF_ENABLED(x) (((x) & 0x1) << 7) 657 #define SMBIOS_CACHE_CONF_OPERATION_MODE(x) (((x) & 0x3) << 8) 658 659 /* defines for max_cache_size and installed_size */ 660 661 #define SMBIOS_CACHE_SIZE_UNIT_1KB (0 << 15) 662 #define SMBIOS_CACHE_SIZE_UNIT_64KB (1 << 15) 663 #define SMBIOS_CACHE_SIZE_MASK 0x7fff 664 #define SMBIOS_CACHE_SIZE_OVERFLOW 0xffff 665 666 #define SMBIOS_CACHE_SIZE2_UNIT_1KB (0 << 31) 667 #define SMBIOS_CACHE_SIZE2_UNIT_64KB (1UL << 31) 668 #define SMBIOS_CACHE_SIZE2_MASK 0x7fffffff 669 670 /* define for cache operation mode */ 671 672 #define SMBIOS_CACHE_OP_MODE_WRITE_THROUGH 0 673 #define SMBIOS_CACHE_OP_MODE_WRITE_BACK 1 674 #define SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS 2 675 #define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 676 677 struct smbios_type7 { 678 struct smbios_header header; 679 u8 socket_designation; 680 u16 cache_configuration; 681 u16 max_cache_size; 682 u16 installed_size; 683 u16 supported_sram_type; 684 u16 current_sram_type; 685 u8 cache_speed; 686 u8 error_correction_type; 687 u8 system_cache_type; 688 u8 associativity; 689 u32 max_cache_size2; 690 u32 installed_size2; 691 u8 eos[2]; 692 } __packed; 693 694 /* enum for connector types */ 695 typedef enum { 696 CONN_NONE = 0x00, 697 CONN_CENTRONICS = 0x01, 698 CONN_MINI_CENTRONICS = 0x02, 699 CONN_PROPRIETARY = 0x03, 700 CONN_DB_25_PIN_MALE = 0x04, 701 CONN_DB_25_PIN_FEMALE = 0x05, 702 CONN_DB_15_PIN_MALE = 0x06, 703 CONN_DB_15_PIN_FEMALE = 0x07, 704 CONN_DB_9_PIN_MALE = 0x08, 705 CONN_DB_9_PIN_FEMALE = 0x09, 706 CONN_RJ_11 = 0x0A, 707 CONN_RJ_45 = 0x0B, 708 CONN_50_PIN_MINI_SCSI = 0x0C, 709 CONN_MINI_DIN = 0x0D, 710 CONN_MICRO_DIN = 0x0E, 711 CONN_PS_2 = 0x0F, 712 CONN_INFRARED = 0x10, 713 CONN_HP_HIL = 0x11, 714 CONN_ACCESS_BUS_USB = 0x12, 715 CONN_SSA_SCSI = 0x13, 716 CONN_CIRCULAR_DIN_8_MALE = 0x14, 717 CONN_CIRCULAR_DIN_8_FEMALE = 0x15, 718 CONN_ON_BOARD_IDE = 0x16, 719 CONN_ON_BOARD_FLOPPY = 0x17, 720 CONN_9_PIN_DUAL_INLINE = 0x18, 721 CONN_25_PIN_DUAL_INLINE = 0x19, 722 CONN_50_PIN_DUAL_INLINE = 0x1A, 723 CONN_68_PIN_DUAL_INLINE = 0x1B, 724 CONN_ON_BOARD_SOUND_INPUT_FROM_CD_ROM = 0x1C, 725 CONN_MINI_CENTRONICS_TYPE14 = 0x1D, 726 CONN_MINI_CENTRONICS_TYPE26 = 0x1E, 727 CONN_MINI_JACK_HEADPHONES = 0x1F, 728 CONN_BNC = 0x20, 729 CONN_1394 = 0x21, 730 CONN_SAS_SATA = 0x22, 731 CONN_USB_TYPE_C = 0x23, 732 CONN_PC_98 = 0xA0, 733 CONN_PC_98_HIRESO = 0xA1, 734 CONN_PC_H98 = 0xA2, 735 CONN_PC98_NOTE = 0xA3, 736 CONN_PC_98_FULL = 0xA4, 737 CONN_OTHER = 0xFF, 738 } type8_connector_types; 739 740 /* enum for port types */ 741 typedef enum { 742 TYPE_NONE_PORT = 0x00, 743 TYPE_PARALLEL_PORT_XT_AT_COMPATIBLE = 0x01, 744 TYPE_PARALLEL_PORT_PS_2 = 0x02, 745 TYPE_PARALLEL_PORT_ECP = 0x03, 746 TYPE_PARALLEL_PORT_EPP = 0x04, 747 TYPE_PARALLEL_PORT_ECP_EPP = 0x05, 748 TYPE_SERIAL_PORT_XT_AT_COMPATIBLE = 0x06, 749 TYPE_SERIAL_PORT_16450_COMPATIBLE = 0x07, 750 TYPE_SERIAL_PORT_16550_COMPATIBLE = 0x08, 751 TYPE_SERIAL_PORT_16550A_COMPATIBLE = 0x09, 752 TYPE_SCSI_PORT = 0x0A, 753 TYPE_MIDI_PORT = 0x0B, 754 TYPE_JOY_STICK_PORT = 0x0C, 755 TYPE_KEYBOARD_PORT = 0x0D, 756 TYPE_MOUSE_PORT = 0x0E, 757 TYPE_SSA_SCSI = 0x0F, 758 TYPE_USB = 0x10, 759 TYPE_FIREWIRE_IEEE_P1394 = 0x11, 760 TYPE_PCMCIA_TYPE_I = 0x12, 761 TYPE_PCMCIA_TYPE_II = 0x13, 762 TYPE_PCMCIA_TYPE_III = 0x14, 763 TYPE_CARDBUS = 0x15, 764 TYPE_ACCESS_BUS_PORT = 0x16, 765 TYPE_SCSI_II = 0x17, 766 TYPE_SCSI_WIDE = 0x18, 767 TYPE_PC_98 = 0x19, 768 TYPE_PC_98_HIRESO = 0x1A, 769 TYPE_PC_H98 = 0x1B, 770 TYPE_VIDEO_PORT = 0x1C, 771 TYPE_AUDIO_PORT = 0x1D, 772 TYPE_MODEM_PORT = 0x1E, 773 TYPE_NETWORK_PORT = 0x1F, 774 TYPE_SATA = 0x20, 775 TYPE_SAS = 0x21, 776 TYPE_MFDP = 0x22, 777 TYPE_THUNDERBOLT = 0x23, 778 TYPE_8251_COMPATIBLE = 0xA0, 779 TYPE_8251_FIFO_COMPATIBLE = 0xA1, 780 TYPE_OTHER_PORT = 0xFF, 781 } type8_port_types; 782 783 struct port_information { 784 const char *internal_reference_designator; 785 type8_connector_types internal_connector_type; 786 const char *external_reference_designator; 787 type8_connector_types external_connector_type; 788 type8_port_types port_type; 789 }; 790 791 struct smbios_type8 { 792 struct smbios_header header; 793 u8 internal_reference_designator; 794 u8 internal_connector_type; 795 u8 external_reference_designator; 796 u8 external_connector_type; 797 u8 port_type; 798 u8 eos[2]; 799 } __packed; 800 801 /* System Slots - Slot Type */ 802 enum misc_slot_type { 803 SlotTypeOther = 0x01, 804 SlotTypeUnknown = 0x02, 805 SlotTypeIsa = 0x03, 806 SlotTypeMca = 0x04, 807 SlotTypeEisa = 0x05, 808 SlotTypePci = 0x06, 809 SlotTypePcmcia = 0x07, 810 SlotTypeVlVesa = 0x08, 811 SlotTypeProprietary = 0x09, 812 SlotTypeProcessorCardSlot = 0x0A, 813 SlotTypeProprietaryMemoryCardSlot = 0x0B, 814 SlotTypeIORiserCardSlot = 0x0C, 815 SlotTypeNuBus = 0x0D, 816 SlotTypePci66MhzCapable = 0x0E, 817 SlotTypeAgp = 0x0F, 818 SlotTypeApg2X = 0x10, 819 SlotTypeAgp4X = 0x11, 820 SlotTypePciX = 0x12, 821 SlotTypeAgp8X = 0x13, 822 SlotTypeM2Socket1_DP = 0x14, 823 SlotTypeM2Socket1_SD = 0x15, 824 SlotTypeM2Socket2 = 0x16, 825 SlotTypeM2Socket3 = 0x17, 826 SlotTypeMxmTypeI = 0x18, 827 SlotTypeMxmTypeII = 0x19, 828 SlotTypeMxmTypeIIIStandard = 0x1A, 829 SlotTypeMxmTypeIIIHe = 0x1B, 830 SlotTypeMxmTypeIV = 0x1C, 831 SlotTypeMxm30TypeA = 0x1D, 832 SlotTypeMxm30TypeB = 0x1E, 833 SlotTypePciExpressGen2Sff_8639 = 0x1F, 834 SlotTypePciExpressGen3Sff_8639 = 0x20, 835 SlotTypePciExpressMini52pinWithBSKO = 0x21, 836 SlotTypePciExpressMini52pinWithoutBSKO = 0x22, 837 SlotTypePciExpressMini76pin = 0x23, 838 SlotTypePciExpressOCPNIC30SFF = 0x26, 839 SlotTypePC98C20 = 0xA0, 840 SlotTypePC98C24 = 0xA1, 841 SlotTypePC98E = 0xA2, 842 SlotTypePC98LocalBus = 0xA3, 843 SlotTypePC98Card = 0xA4, 844 SlotTypePciExpress = 0xA5, 845 SlotTypePciExpressX1 = 0xA6, 846 SlotTypePciExpressX2 = 0xA7, 847 SlotTypePciExpressX4 = 0xA8, 848 SlotTypePciExpressX8 = 0xA9, 849 SlotTypePciExpressX16 = 0xAA, 850 SlotTypePciExpressGen2 = 0xAB, 851 SlotTypePciExpressGen2X1 = 0xAC, 852 SlotTypePciExpressGen2X2 = 0xAD, 853 SlotTypePciExpressGen2X4 = 0xAE, 854 SlotTypePciExpressGen2X8 = 0xAF, 855 SlotTypePciExpressGen2X16 = 0xB0, 856 SlotTypePciExpressGen3 = 0xB1, 857 SlotTypePciExpressGen3X1 = 0xB2, 858 SlotTypePciExpressGen3X2 = 0xB3, 859 SlotTypePciExpressGen3X4 = 0xB4, 860 SlotTypePciExpressGen3X8 = 0xB5, 861 SlotTypePciExpressGen3X16 = 0xB6, 862 SlotTypePciExpressGen4 = 0xB8, 863 SlotTypePciExpressGen4x1 = 0xB9, 864 SlotTypePciExpressGen4x2 = 0xBA, 865 SlotTypePciExpressGen4x4 = 0xBB, 866 SlotTypePciExpressGen4x8 = 0xBC, 867 SlotTypePciExpressGen4x16 = 0xBD, 868 SlotTypePciExpressGen5 = 0xBE, 869 SlotTypePciExpressGen5x1 = 0xBF, 870 SlotTypePciExpressGen5x2 = 0xC0, 871 SlotTypePciExpressGen5x4 = 0xC1, 872 SlotTypePciExpressGen5x8 = 0xC2, 873 SlotTypePciExpressGen5x16 = 0xC3, 874 SlotTypePciExpressGen6AndBeyond = 0xC4, 875 SlotTypeEDSFF_E1 = 0xC5, 876 SlotTypeEDSFF_E3 = 0xC6, 877 }; 878 879 /* System Slots - Slot Data Bus Width. */ 880 enum slot_data_bus_bandwidth { 881 SlotDataBusWidthOther = 0x01, 882 SlotDataBusWidthUnknown = 0x02, 883 SlotDataBusWidth8Bit = 0x03, 884 SlotDataBusWidth16Bit = 0x04, 885 SlotDataBusWidth32Bit = 0x05, 886 SlotDataBusWidth64Bit = 0x06, 887 SlotDataBusWidth128Bit = 0x07, 888 SlotDataBusWidth1X = 0x08, 889 SlotDataBusWidth2X = 0x09, 890 SlotDataBusWidth4X = 0x0A, 891 SlotDataBusWidth8X = 0x0B, 892 SlotDataBusWidth12X = 0x0C, 893 SlotDataBusWidth16X = 0x0D, 894 SlotDataBusWidth32X = 0x0E 895 }; 896 897 /* System Slots - Current Usage. */ 898 enum misc_slot_usage { 899 SlotUsageOther = 0x01, 900 SlotUsageUnknown = 0x02, 901 SlotUsageAvailable = 0x03, 902 SlotUsageInUse = 0x04, 903 SlotUsageUnavailable = 0x05 904 }; 905 906 /* System Slots - Slot Length.*/ 907 enum misc_slot_length { 908 SlotLengthOther = 0x01, 909 SlotLengthUnknown = 0x02, 910 SlotLengthShort = 0x03, 911 SlotLengthLong = 0x04 912 }; 913 914 /* System Slots - Slot Characteristics 1. */ 915 #define SMBIOS_SLOT_UNKNOWN (1 << 0) 916 #define SMBIOS_SLOT_5V (1 << 1) 917 #define SMBIOS_SLOT_3P3V (1 << 2) 918 #define SMBIOS_SLOT_SHARED (1 << 3) 919 #define SMBIOS_SLOT_PCCARD_16 (1 << 4) 920 #define SMBIOS_SLOT_PCCARD_CARDBUS (1 << 5) 921 #define SMBIOS_SLOT_PCCARD_ZOOM (1 << 6) 922 #define SMBIOS_SLOT_PCCARD_MODEM_RING (1 << 7) 923 /* System Slots - Slot Characteristics 2. */ 924 #define SMBIOS_SLOT_PME (1 << 0) 925 #define SMBIOS_SLOT_HOTPLUG (1 << 1) 926 #define SMBIOS_SLOT_SMBUS (1 << 2) 927 #define SMBIOS_SLOT_BIFURCATION (1 << 3) 928 929 struct slot_peer_groups { 930 u16 peer_seg_num; 931 u8 peer_bus_num; 932 u8 peer_dev_fn_num; 933 u8 peer_data_bus_width; 934 } __packed; 935 936 struct smbios_type9 { 937 struct smbios_header header; 938 u8 slot_designation; 939 u8 slot_type; 940 u8 slot_data_bus_width; 941 u8 current_usage; 942 u8 slot_length; 943 u16 slot_id; 944 u8 slot_characteristics_1; 945 u8 slot_characteristics_2; 946 u16 segment_group_number; 947 u8 bus_number; 948 u8 device_function_number; 949 u8 data_bus_width; 950 u8 peer_group_count; 951 struct slot_peer_groups peer[0]; 952 u8 eos[2]; 953 } __packed; 954 955 struct smbios_type11 { 956 struct smbios_header header; 957 u8 count; 958 u8 eos[2]; 959 } __packed; 960 961 struct smbios_type15 { 962 struct smbios_header header; 963 u16 area_length; 964 u16 header_offset; 965 u16 data_offset; 966 u8 access_method; 967 u8 log_status; 968 u32 change_token; 969 u32 address; 970 u8 header_format; 971 u8 log_type_descriptors; 972 u8 log_type_descriptor_length; 973 u8 eos[2]; 974 } __packed; 975 976 enum { 977 SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0, 978 SMBIOS_EVENTLOG_ACCESS_METHOD_IO8X2, 979 SMBIOS_EVENTLOG_ACCESS_METHOD_IO16, 980 SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32, 981 SMBIOS_EVENTLOG_ACCESS_METHOD_GPNV, 982 }; 983 984 enum { 985 SMBIOS_EVENTLOG_STATUS_VALID = 1, /* Bit 0 */ 986 SMBIOS_EVENTLOG_STATUS_FULL = 2, /* Bit 1 */ 987 }; 988 989 #define SMBIOS_USE_EXTENDED_MAX_CAPACITY (1ULL << 31) 990 991 struct smbios_type16 { 992 struct smbios_header header; 993 u8 location; 994 u8 use; 995 u8 memory_error_correction; 996 u32 maximum_capacity; 997 u16 memory_error_information_handle; 998 u16 number_of_memory_devices; 999 u64 extended_maximum_capacity; 1000 u8 eos[2]; 1001 } __packed; 1002 1003 struct smbios_type17 { 1004 struct smbios_header header; 1005 u16 phys_memory_array_handle; 1006 u16 memory_error_information_handle; 1007 u16 total_width; 1008 u16 data_width; 1009 u16 size; 1010 u8 form_factor; 1011 u8 device_set; 1012 u8 device_locator; 1013 u8 bank_locator; 1014 u8 memory_type; 1015 u16 type_detail; 1016 u16 speed; 1017 u8 manufacturer; 1018 u8 serial_number; 1019 u8 asset_tag; 1020 u8 part_number; 1021 u8 attributes; 1022 u32 extended_size; 1023 u16 clock_speed; 1024 u16 minimum_voltage; 1025 u16 maximum_voltage; 1026 u16 configured_voltage; 1027 u8 eos[2]; 1028 } __packed; 1029 1030 struct smbios_type19 { 1031 struct smbios_header header; 1032 u32 starting_address; 1033 u32 ending_address; 1034 u16 memory_array_handle; 1035 u8 partition_width; 1036 u64 extended_starting_address; 1037 u64 extended_ending_address; 1038 u8 eos[2]; 1039 } __packed; 1040 1041 struct smbios_type20 { 1042 struct smbios_header header; 1043 u32 addr_start; 1044 u32 addr_end; 1045 u16 memory_device_handle; 1046 u16 memory_array_mapped_address_handle; 1047 u8 partition_row_pos; 1048 u8 interleave_pos; 1049 u8 interleave_depth; 1050 u64 ext_addr_start; 1051 u64 ext_addr_end; 1052 u8 eos[2]; 1053 } __packed; 1054 1055 /* Bit[7..5] = Temp status */ 1056 enum smbios_temp_status { 1057 SMBIOS_TEMP_STATUS_OTHER = 0x01, 1058 SMBIOS_TEMP_STATUS_UNKNOWN, 1059 SMBIOS_TEMP_STATUS_OK, 1060 SMBIOS_TEMP_STATUS_NONCRITICAL, 1061 SMBIOS_TEMP_STATUS_CRITICAL, 1062 SMBIOS_TEMP_STATUS_NONREC, // Non-Recoverable. 1063 }; 1064 1065 /* Bit[4..0] = Temp location */ 1066 enum smbios_temp_location { 1067 SMBIOS_TEMP_LOCATION_OTHER = 0x01, 1068 SMBIOS_TEMP_LOCATION_UNKNOWN, 1069 SMBIOS_TEMP_LOCATION_PROCESSOR, 1070 SMBIOS_TEMP_LOCATION_DISK, 1071 SMBIOS_TEMP_LOCATION_BAY, // Peripheral Bay. 1072 SMBIOS_TEMP_LOCATION_SMM, // System Management Module. 1073 SMBIOS_TEMP_LOCATION_BOARD, // Motherboard. 1074 SMBIOS_TEMP_LOCATION_MM, // Memory. 1075 SMBIOS_TEMP_LOCATION_PM, // Processor Module. 1076 SMBIOS_TEMP_LOCATION_POW, // Power Unit. 1077 SMBIOS_TEMP_LOCATION_ADDCARD, 1078 }; 1079 1080 struct smbios_type28 { 1081 struct smbios_header header; 1082 u8 description; 1083 u8 location_and_status; 1084 u16 maximum_value; 1085 u16 minimum_value; 1086 u16 resolution; 1087 u16 tolerance; 1088 u16 accuracy; 1089 u32 oem_defined; 1090 u16 nominal_value; 1091 u8 eos[2]; 1092 } __packed; 1093 1094 1095 struct smbios_type32 { 1096 struct smbios_header header; 1097 u8 reserved[6]; 1098 u8 boot_status; 1099 u8 eos[2]; 1100 } __packed; 1101 1102 struct smbios_type38 { 1103 struct smbios_header header; 1104 u8 interface_type; 1105 u8 ipmi_rev; 1106 u8 i2c_slave_addr; 1107 u8 nv_storage_addr; 1108 u64 base_address; 1109 u8 base_address_modifier; 1110 u8 irq; 1111 u8 eos[2]; 1112 } __packed; 1113 1114 enum smbios_bmc_interface_type { 1115 SMBIOS_BMC_INTERFACE_UNKNOWN = 0, 1116 SMBIOS_BMC_INTERFACE_KCS, 1117 SMBIOS_BMC_INTERFACE_SMIC, 1118 SMBIOS_BMC_INTERFACE_BLOCK, 1119 SMBIOS_BMC_INTERFACE_SMBUS, 1120 }; 1121 1122 typedef enum { 1123 PowerSupplyTypeOther = 1, 1124 PowerSupplyTypeUnknown = 2, 1125 PowerSupplyTypeLinear = 3, 1126 PowerSupplyTypeSwitching = 4, 1127 PowerSupplyTypeBattery = 5, 1128 PowerSupplyTypeUps = 6, 1129 PowerSupplyTypeConverter = 7, 1130 PowerSupplyTypeRegulator = 8 1131 } power_supply_type; 1132 1133 typedef enum { 1134 PowerSupplyStatusOther = 1, 1135 PowerSupplyStatusUnknown = 2, 1136 PowerSupplyStatusOk = 3, 1137 PowerSupplyStatusNonCritical = 4, 1138 PowerSupplyStatusCritical = 5 1139 } power_supply_status; 1140 1141 typedef enum { 1142 PowerSupplyInputVoltageRangeSwitchingOther = 1, 1143 PowerSupplyInputVoltageRangeSwitchingUnknown = 2, 1144 PowerSupplyInputVoltageRangeSwitchingManual = 3, 1145 PowerSupplyInputVoltageRangeSwitchingAutoSwitch = 4, 1146 PowerSupplyInputVoltageRangeSwitchingWideRange = 5, 1147 PowerSupplyInputVoltageRangeSwitchingNotApplicable = 6 1148 } power_supply_input_voltage_range_switching; 1149 1150 struct power_supply_ch { 1151 u16 reserved :2; 1152 u16 power_supply_type :4; 1153 u16 power_supply_status :3; 1154 u16 input_voltage_range_switch :4; 1155 u16 power_supply_unplugged :1; 1156 u16 power_supply_present :1; 1157 u16 power_supply_hot_replaceble :1; 1158 }; 1159 1160 struct smbios_type39 { 1161 struct smbios_header header; 1162 u8 power_unit_group; 1163 u8 location; 1164 u8 device_name; 1165 u8 manufacturer; 1166 u8 serial_number; 1167 u8 asset_tag_number; 1168 u8 model_part_number; 1169 u8 revision_level; 1170 u16 max_power_capacity; 1171 u16 power_supply_characteristics; 1172 u16 input_voltage_probe_handle; 1173 u16 cooling_device_handle; 1174 u16 input_current_probe_handle; 1175 u8 eos[2]; 1176 } __packed; 1177 1178 int smbios_write_type39(unsigned long *current, int *handle, 1179 u8 unit_group, const char *loc, const char *dev_name, 1180 const char *man, const char *serial_num, 1181 const char *tag_num, const char *part_num, 1182 const char *rev_lvl, u16 max_pow_cap, 1183 const struct power_supply_ch *ps_ch); 1184 1185 typedef enum { 1186 SMBIOS_DEVICE_TYPE_OTHER = 0x01, 1187 SMBIOS_DEVICE_TYPE_UNKNOWN, 1188 SMBIOS_DEVICE_TYPE_VIDEO, 1189 SMBIOS_DEVICE_TYPE_SCSI, 1190 SMBIOS_DEVICE_TYPE_ETHERNET, 1191 SMBIOS_DEVICE_TYPE_TOKEN_RING, 1192 SMBIOS_DEVICE_TYPE_SOUND, 1193 SMBIOS_DEVICE_TYPE_PATA, 1194 SMBIOS_DEVICE_TYPE_SATA, 1195 SMBIOS_DEVICE_TYPE_SAS, 1196 SMBIOS_DEVICE_TYPE_WIRELESS_LAN, 1197 SMBIOS_DEVICE_TYPE_BLUETOOTH, 1198 SMBIOS_DEVICE_TYPE_WWAN, 1199 SMBIOS_DEVICE_TYPE_EMMC, 1200 SMBIOS_DEVICE_TYPE_NVME, 1201 SMBIOS_DEVICE_TYPE_UFS, 1202 } smbios_onboard_device_type; 1203 1204 #define SMBIOS_DEVICE_TYPE_COUNT 10 1205 1206 struct smbios_type41 { 1207 struct smbios_header header; 1208 u8 reference_designation; 1209 u8 device_type: 7; 1210 u8 device_status: 1; 1211 u8 device_type_instance; 1212 u16 segment_group_number; 1213 u8 bus_number; 1214 u8 function_number: 3; 1215 u8 device_number: 5; 1216 u8 eos[2]; 1217 } __packed; 1218 1219 1220 #define SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED (1ULL << 2) 1221 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_FW_UPD (1ULL << 3) 1222 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_PLATFORM_SW_SUPPORT (1ULL << 4) 1223 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_OEM_PROPRIETARY (1ULL << 5) 1224 1225 struct smbios_type43 { 1226 struct smbios_header header; 1227 u32 vendor_id; 1228 u8 major_spec_ver; 1229 u8 minor_spec_ver; 1230 u32 fw_ver1; 1231 u32 fw_ver2; 1232 u8 description; 1233 u64 characteristics; 1234 u32 oem_defined; 1235 u8 eos[2]; 1236 } __packed; 1237 1238 struct smbios_type127 { 1239 struct smbios_header header; 1240 u8 eos[2]; 1241 } __packed; 1242 1243 /* Provided to help architecture code */ 1244 int smbios_write_type7(unsigned long *current, 1245 const int handle, 1246 const u8 level, 1247 const u8 sram_type, 1248 const enum smbios_cache_associativity associativity, 1249 const enum smbios_cache_type type, 1250 const size_t max_cache_size, 1251 const size_t cache_size); 1252 enum smbios_cache_associativity smbios_cache_associativity(const u8 num); 1253 1254 /* Must be defined by architecture code */ 1255 int smbios_write_type4(unsigned long *current, int handle); 1256 int smbios_write_type7_cache_parameters(unsigned long *current, 1257 int *handle, 1258 int *max_struct_size, 1259 struct smbios_type4 *type4); 1260 1261 void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, 1262 struct smbios_type17 *t); 1263 void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, 1264 struct smbios_type17 *t); 1265 void smbios_fill_dimm_locator(const struct dimm_info *dimm, 1266 struct smbios_type17 *t); 1267 1268 smbios_wakeup_type smbios_system_wakeup_type(void); 1269 smbios_board_type smbios_mainboard_board_type(void); 1270 smbios_enclosure_type smbios_mainboard_enclosure_type(void); 1271 1272 #endif