1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #include <device/mmio.h>
 4  #include <bootblock_common.h>
 5  #include <device/i2c_simple.h>
 6  #include <gpio.h>
 7  #include <soc/addressmap.h>
 8  #include <soc/clk_rst.h>
 9  #include <soc/clock.h>
10  #include <soc/nvidia/tegra/i2c.h>
11  #include <soc/pinmux.h>
12  #include <soc/spi.h>	/* FIXME: move back to soc code? */
13  
14  #include "pmic.h"
15  
16  static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
17  
18  static void set_clock_sources(void)
19  {
20  	/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
21  	write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
22  
23  	clock_configure_source(mselect, PLLP, 102000);
24  
25  	/* The PMIC is on I2C5 and can run at 400 KHz. */
26  	clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
27  
28  	/* TODO: We should be able to set this to 50MHz, but that did not seem
29  	 * reliable. */
30  	clock_configure_source(sbc4, PLLP, 33333);
31  }
32  
33  void bootblock_mainboard_init(void)
34  {
35  	set_clock_sources();
36  
37  	clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
38  				 CLK_H_I2C5 | CLK_H_APBDMA,
39  				 0, CLK_V_MSELECT, 0, 0);
40  
41  	// Board ID GPIOs, bits 0-3.
42  	gpio_input(GPIO(Q3));
43  	gpio_input(GPIO(T1));
44  	gpio_input(GPIO(X1));
45  	gpio_input(GPIO(X4));
46  
47  	// I2C5 (PMU) clock.
48  	pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
49  			  PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
50  	// I2C5 (PMU) data.
51  	pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
52  			  PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
53  	i2c_init(4);
54  	pmic_init(4);
55  
56  	/* SPI4 data out (MOSI) */
57  	pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
58  			  PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
59  			  PINMUX_PULL_UP);
60  	/* SPI4 data in (MISO) */
61  	pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
62  			  PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
63  			  PINMUX_PULL_UP);
64  	/* SPI4 clock */
65  	pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
66  			  PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
67  	/* SPI4 chip select 0 */
68  	pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
69  			  PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
70  
71  	tegra_spi_init(4);
72  }