1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #include <console/console.h>
 4  #include <delay.h>
 5  #include <device/i2c_simple.h>
 6  #include <stdint.h>
 7  #include <reset.h>
 8  
 9  #include "pmic.h"
10  
11  enum {
12  	AS3722_I2C_ADDR = 0x40
13  };
14  
15  struct as3722_init_reg {
16  	u8 reg;
17  	u8 val;
18  	u8 delay;
19  };
20  
21  static struct as3722_init_reg init_list[] = {
22  	{AS3722_SDO0, 0x3C, 1},
23  	{AS3722_SDO1, 0x32, 0},
24  	{AS3722_LDO3, 0x59, 0},
25  	{AS3722_SDO2, 0x3C, 0},
26  	{AS3722_SDO3, 0x00, 0},
27  	{AS3722_SDO4, 0x00, 0},
28  	{AS3722_SDO5, 0x50, 0},
29  	{AS3722_SDO6, 0x28, 1},
30  	{AS3722_LDO0, 0x8A, 0},
31  	{AS3722_LDO1, 0x00, 0},
32  	{AS3722_LDO2, 0x10, 0},
33  	{AS3722_LDO4, 0x00, 0},
34  	{AS3722_LDO5, 0x00, 0},
35  	{AS3722_LDO6, 0x00, 0},
36  	{AS3722_LDO7, 0x00, 0},
37  	{AS3722_LDO9, 0x00, 0},
38  	{AS3722_LDO10, 0x00, 0},
39  	{AS3722_LDO11, 0x00, 1},
40  };
41  
42  static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int do_delay)
43  {
44  	if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
45  		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
46  			__func__, reg, val);
47  		/* Reset the SoC on any PMIC write error */
48  		board_reset();
49  	} else {
50  		if (do_delay)
51  			udelay(500);
52  	}
53  }
54  
55  static void pmic_slam_defaults(unsigned int bus)
56  {
57  	int i;
58  
59  	for (i = 0; i < ARRAY_SIZE(init_list); i++) {
60  		struct as3722_init_reg *reg = &init_list[i];
61  		pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
62  	}
63  }
64  
65  void pmic_init(unsigned int bus)
66  {
67  	/*
68  	 * Don't need to set up VDD_CORE - already done - by OTP
69  	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
70  	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
71  	 */
72  
73  	/* Restore PMIC POR defaults, in case kernel changed 'em */
74  	pmic_slam_defaults(bus);
75  
76  	/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
77  	pmic_write_reg(bus, 0x00, 0x50, 1);
78  
79  	/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
80  	pmic_write_reg(bus, 0x06, 0x28, 1);
81  
82  	/*
83  	 * First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
84  	 * regulator.
85  	 */
86  	pmic_write_reg(bus, 0x12, 0x10, 1);
87  
88  	/*
89  	 * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
90  	 * the value (register 0x20 bit 4)
91  	 */
92  	pmic_write_reg(bus, 0x0c, 0x07, 0);
93  	pmic_write_reg(bus, 0x20, 0x10, 1);
94  }