1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #include <bootblock_common.h>
 4  #include <device/pci_def.h>
 5  #include <device/pci_ops.h>
 6  #include <intelblocks/lpc_lib.h>
 7  #include <intelblocks/pcr.h>
 8  #include <soc/pci_devs.h>
 9  #include <soc/pcr_ids.h>
10  #include <soc/intel/common/block/lpc/lpc_def.h>
11  #include <superio/aspeed/ast2400/ast2400.h>
12  #include <superio/aspeed/common/aspeed.h>
13  
14  #define ASPEED_SIO_PORT 0x2E
15  
16  static void enable_espi_lpc_io_windows(void)
17  {
18  	/*
19  	 * Set up decoding windows on PCH over PCR. The CPUs use two of AST2600 SIO ports,
20  	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
21  	 * For Whitestone-2, only SUART1 is used.
22  	 * Enable com1 (0x3f8), com2 (0x2f8) and superio (0x2e)
23  	 */
24  	lpc_open_pmio_window(0x3f8, 8);
25  	lpc_open_pmio_window(0x2f8, 8);
26  	lpc_open_pmio_window(0x2e, 2);
27  	lpc_io_setup_comm_a_b();
28  }
29  
30  static uint8_t com_to_ast_sio(uint8_t com)
31  {
32  	switch (com) {
33  	case 0:
34  		return AST2400_SUART1;
35  	case 1:
36  		return AST2400_SUART2;
37  	case 2:
38  		return AST2400_SUART3;
39  	case 4:
40  		return AST2400_SUART4;
41  	default:
42  		return AST2400_SUART1;
43  	}
44  }
45  
46  void bootblock_mainboard_early_init(void)
47  {
48  	/* Open IO windows */
49  	enable_espi_lpc_io_windows();
50  
51  	/* Configure appropriate physical port of SuperIO chip off BMC */
52  	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
53  		com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
54  	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
55  }