1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
 4  #define NORTHBRIDGE_INTEL_GM45_CHIP_H
 5  
 6  #include <drivers/intel/gma/i915.h>
 7  
 8  struct northbridge_intel_gm45_config {
 9  	u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
10  	u16 gpu_panel_power_down_delay;          /* T3 time sequence */
11  	u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
12  	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
13  	u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
14  	struct i915_gpu_controller_info gfx;
15  	u16 default_pwm_freq;
16  	u8 duty_cycle;
17  
18  	/*
19  	 * Maximum PCI mmio size in MiB.
20  	 */
21  	u16 pci_mmio_size;
22  	int slfm;
23  };
24  
25  #endif				/* NORTHBRIDGE_INTEL_GM45_CHIP_H */