gma.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <device/mmio.h> 4 #include <console/console.h> 5 #include <device/device.h> 6 #include <device/pci.h> 7 #include <device/pci_ids.h> 8 #include <drivers/intel/gma/edid.h> 9 #include <drivers/intel/gma/opregion.h> 10 #include <drivers/intel/gma/libgfxinit.h> 11 #include <string.h> 12 #include <device/pci_ops.h> 13 #include <commonlib/helpers.h> 14 #include <types.h> 15 16 #include "drivers/intel/gma/i915_reg.h" 17 #include "chip.h" 18 #include "gm45.h" 19 20 static struct resource *gtt_res = NULL; 21 22 u32 gtt_read(u32 reg) 23 { 24 return read32(res2mmio(gtt_res, reg, 0)); 25 } 26 27 void gtt_write(u32 reg, u32 data) 28 { 29 write32(res2mmio(gtt_res, reg, 0), data); 30 } 31 32 static const char *gm45_get_lvds_edid_str(void) 33 { 34 u8 *mmio; 35 u8 edid_data_lvds[128]; 36 struct edid edid_lvds; 37 static char edid_str[EDID_ASCII_STRING_LENGTH + 1]; 38 39 if (edid_str[0]) 40 return edid_str; 41 if (!gtt_res) { 42 printk(BIOS_ERR, "Never call %s() outside dev.init() context.\n", __func__); 43 return NULL; 44 } 45 mmio = res2mmio(gtt_res, 0, 0); 46 47 printk(BIOS_DEBUG, "LVDS EDID\n"); 48 intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, 49 edid_data_lvds, sizeof(edid_data_lvds)); 50 intel_gmbus_stop(mmio + GMBUS0); 51 52 if (decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds) 53 != EDID_CONFORMANT) 54 return NULL; 55 memcpy(edid_str, edid_lvds.ascii_string, sizeof(edid_str)); 56 return edid_str; 57 } 58 59 static u32 get_cdclk(struct device *const dev) 60 { 61 const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; 62 63 switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) { 64 case VCO_2666: 65 case VCO_4000: 66 case VCO_5333: 67 return cdclk_sel ? 333333333 : 222222222; 68 case VCO_3200: 69 return cdclk_sel ? 320000000 : 228571429; 70 default: 71 printk(BIOS_WARNING, 72 "Unknown VCO frequency, using default cdclk.\n"); 73 return 222222222; 74 } 75 } 76 77 static u32 freq_to_blc_pwm_ctl(struct device *const dev, 78 u16 pwm_freq, u8 duty_perc) 79 { 80 u32 blc_mod; 81 82 blc_mod = get_cdclk(dev) / (128 * pwm_freq); 83 84 if (duty_perc <= 100) 85 return (blc_mod << 16) | (blc_mod * duty_perc / 100); 86 else 87 return (blc_mod << 16) | blc_mod; 88 } 89 90 u16 get_blc_pwm_freq_value(void) 91 { 92 static u16 blc_pwm_freq; 93 const struct blc_pwm_t *blc_pwm; 94 int i; 95 int blc_array_len; 96 97 if (blc_pwm_freq > 0) 98 return blc_pwm_freq; 99 100 const char *const edid_ascii_string = gm45_get_lvds_edid_str(); 101 if (!edid_ascii_string) { 102 printk(BIOS_ERR, "Need LVDS EDID string to derive backlight PWM frequency!\n"); 103 return 0; 104 } 105 106 blc_array_len = get_blc_values(&blc_pwm); 107 /* Find EDID string and pwm freq in lookup table */ 108 for (i = 0; i < blc_array_len; i++) { 109 if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { 110 blc_pwm_freq = blc_pwm[i].pwm_freq; 111 printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", 112 blc_pwm[i].ascii_string, blc_pwm_freq); 113 break; 114 } 115 } 116 117 if (i == blc_array_len) 118 printk(BIOS_NOTICE, "Your panel's EDID `%s` wasn't found in the lookup table.\n" 119 "You may have issues with your panel's backlight.\n" 120 "If you want to help improving coreboot please report: this EDID string\n" 121 "and the result of `intel_reg read BLC_PWM_CTL` (from intel-gpu-tools)\n" 122 "while running vendor BIOS\n", 123 edid_ascii_string); 124 125 return blc_pwm_freq; 126 } 127 128 static void gma_pm_init_post_vbios(struct device *const dev) 129 { 130 const struct northbridge_intel_gm45_config *const conf = dev->chip_info; 131 132 u32 reg32; 133 u8 reg8; 134 u16 pwm_freq; 135 136 /* Setup Panel Power On Delays */ 137 reg32 = gtt_read(PP_ON_DELAYS); 138 if (!reg32) { 139 reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; 140 reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); 141 gtt_write(PP_ON_DELAYS, reg32); 142 } 143 144 /* Setup Panel Power Off Delays */ 145 reg32 = gtt_read(PP_OFF_DELAYS); 146 if (!reg32) { 147 reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; 148 reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); 149 gtt_write(PP_OFF_DELAYS, reg32); 150 } 151 152 /* Setup Panel Power Cycle Delay */ 153 if (conf->gpu_panel_power_cycle_delay) { 154 reg32 = (get_cdclk(dev) / 20000 - 1) 155 << PP_REFERENCE_DIVIDER_SHIFT; 156 reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; 157 gtt_write(PP_DIVISOR, reg32); 158 } 159 160 /* Enable Backlight */ 161 gtt_write(BLC_PWM_CTL2, (1 << 31)); 162 reg8 = 100; 163 if (conf->duty_cycle != 0) 164 reg8 = conf->duty_cycle; 165 pwm_freq = get_blc_pwm_freq_value(); 166 if (pwm_freq == 0 && conf->default_pwm_freq != 0) 167 pwm_freq = conf->default_pwm_freq; 168 169 if (pwm_freq == 0) 170 gtt_write(BLC_PWM_CTL, 0x06100610); 171 else 172 gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, pwm_freq, 173 reg8)); 174 } 175 176 static void gma_func0_init(struct device *dev) 177 { 178 const struct northbridge_intel_gm45_config *const conf = dev->chip_info; 179 180 /* Probe MMIO resource first. It's needed even for 181 intel_gma_init_igd_opregion() which may call back. */ 182 gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); 183 if (!gtt_res) 184 return; 185 186 intel_gma_init_igd_opregion(); 187 188 /* 189 * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M 190 * cycles are simply not decoded which is fine. 191 */ 192 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); 193 memset(res2mmio(gtt_res, 2*MiB, 0), 0, 2*MiB); 194 195 if (CONFIG(NO_GFX_INIT)) 196 pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); 197 198 if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { 199 /* PCI Init, will run VBIOS */ 200 printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); 201 pci_dev_init(dev); 202 } 203 204 /* Post VBIOS init */ 205 gma_pm_init_post_vbios(dev); 206 207 if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { 208 int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; 209 if (vga_disable) { 210 printk(BIOS_INFO, 211 "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); 212 } else { 213 int lightup_ok; 214 gma_gfxinit(&lightup_ok); 215 /* Linux relies on VBT for panel info. */ 216 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); 217 } 218 } 219 } 220 221 static void gma_generate_ssdt(const struct device *device) 222 { 223 const struct northbridge_intel_gm45_config *chip = device->chip_info; 224 225 drivers_intel_gma_displays_ssdt_generate(&chip->gfx); 226 } 227 228 static const char *gma_acpi_name(const struct device *dev) 229 { 230 return "GFX0"; 231 } 232 233 static struct device_operations gma_func0_ops = { 234 .read_resources = pci_dev_read_resources, 235 .set_resources = pci_dev_set_resources, 236 .enable_resources = pci_dev_enable_resources, 237 .acpi_fill_ssdt = gma_generate_ssdt, 238 .init = gma_func0_init, 239 .ops_pci = &pci_dev_ops_pci, 240 .acpi_name = gma_acpi_name, 241 }; 242 243 static const unsigned short pci_device_ids[] = 244 { 245 0x2a42, 0 246 }; 247 248 static const struct pci_driver gma __pci_driver = { 249 .ops = &gma_func0_ops, 250 .vendor = PCI_VID_INTEL, 251 .devices = pci_device_ids, 252 };