1  /* SPDX-License-Identifier: GPL-2.0-or-later */
  2  
  3  #ifndef PINEVIEW_RAMINIT_H
  4  #define PINEVIEW_RAMINIT_H
  5  
  6  #define SYSINFO_DIMM_NOT_POPULATED	0x00
  7  #define SYSINFO_DIMM_X16SS		0x01
  8  #define SYSINFO_DIMM_X16DS		0x02
  9  #define SYSINFO_DIMM_X8DS		0x05
 10  #define SYSINFO_DIMM_X8DDS		0x06
 11  
 12  enum fsb_clk {
 13  	FSB_CLOCK_667MHz = 0,
 14  	FSB_CLOCK_800MHz = 1,
 15  };
 16  
 17  enum mem_clk {
 18  	MEM_CLOCK_667MHz = 0,
 19  	MEM_CLOCK_800MHz = 1,
 20  };
 21  
 22  enum ddr {
 23  	DDR2 = 2,
 24  	DDR3 = 3,
 25  };
 26  
 27  enum chip_width { /* as in DDR3 spd */
 28  	CHIP_WIDTH_x4	= 0,
 29  	CHIP_WIDTH_x8	= 1,
 30  	CHIP_WIDTH_x16	= 2,
 31  	CHIP_WIDTH_x32	= 3,
 32  };
 33  
 34  enum chip_cap { /* as in DDR3 spd */
 35  	CHIP_CAP_256M	= 0,
 36  	CHIP_CAP_512M	= 1,
 37  	CHIP_CAP_1G	= 2,
 38  	CHIP_CAP_2G	= 3,
 39  	CHIP_CAP_4G	= 4,
 40  	CHIP_CAP_8G	= 5,
 41  	CHIP_CAP_16G	= 6,
 42  };
 43  
 44  struct timings {
 45  	unsigned int	CAS;
 46  	enum fsb_clk	fsb_clock;
 47  	enum mem_clk	mem_clock;
 48  	unsigned int	tRAS;
 49  	unsigned int	tRP;
 50  	unsigned int	tRCD;
 51  	unsigned int	tWR;
 52  	unsigned int	tRFC;
 53  	unsigned int	tWTR;
 54  	unsigned int	tRRD;
 55  	unsigned int	tRTP;
 56  };
 57  
 58  struct dimminfo {
 59  	unsigned int	card_type; /* 0x0: unpopulated,
 60  				      0xa - 0xf: raw card type A - F */
 61  	u8		type;
 62  	enum chip_width	width;
 63  	enum chip_cap	chip_capacity;
 64  	unsigned int	page_size; /* of whole DIMM in Bytes (4096 or 8192) */
 65  	unsigned int	sides;
 66  	unsigned int	banks;
 67  	unsigned int	ranks;
 68  	unsigned int	rows;
 69  	unsigned int	cols;
 70  	unsigned int	cas_latencies;
 71  	unsigned int	tAAmin;
 72  	unsigned int	tCKmin;
 73  	unsigned int	tWR;
 74  	unsigned int	tRP;
 75  	unsigned int	tRCD;
 76  	unsigned int	tRAS;
 77  	unsigned int	rank_capacity_mb; /* per rank in Megabytes */
 78  	u8		spd_data[256];
 79  };
 80  
 81  struct pllparam {
 82  	u8 kcoarse[2][72];
 83  	u8 pi[2][72];
 84  	u8 dben[2][72];
 85  	u8 dbsel[2][72];
 86  	u8 clkdelay[2][72];
 87  };
 88  
 89  struct sysinfo {
 90  	u8 maxpi;
 91  	u8 pioffset;
 92  	u8 pi[8];
 93  	u16 coarsectrl;
 94  	u16 coarsedelay;
 95  	u16 mediumphase;
 96  	u16 readptrdelay;
 97  
 98  	int		boot_path;
 99  	u16		ggc;
100  
101  	int		dimm_config[2];
102  	int		spd_type;
103  	int		channel_capacity[2];
104  	struct timings	selected_timings;
105  	struct dimminfo	dimms[4];
106  	u8		spd_map[4];
107  
108  	u8 nodll;
109  	u8 async;
110  	u8 dt0mode;
111  };
112  
113  void sdram_initialize(int boot_path, const u8 *sdram_addresses);
114  
115  #endif /* PINEVIEW_RAMINIT_H */