1  /* SPDX-License-Identifier: GPL-2.0-only */
 2  
 3  #include <timestamp.h>
 4  #include <console/console.h>
 5  #include <device/pci_ops.h>
 6  #include <cbmem.h>
 7  #include <cf9_reset.h>
 8  #include <romstage_handoff.h>
 9  #include <southbridge/intel/i82801gx/i82801gx.h>
10  #include <southbridge/intel/common/pmclib.h>
11  #include <arch/romstage.h>
12  #include "raminit.h"
13  #include "pineview.h"
14  
15  static void rcba_config(void)
16  {
17  	/* Set up Virtual Channel 0 */
18  	RCBA32(0x0014) = 0x80000001;
19  	RCBA32(0x001c) = 0x03128010;
20  }
21  
22  __weak void mb_pirq_setup(void)
23  {
24  }
25  
26  /* The romstage entry point for this platform is not mainboard-specific, hence the name. */
27  void mainboard_romstage_entry(void)
28  {
29  	u8 spd_addrmap[4] = {};
30  	int boot_path, cbmem_was_initted;
31  	int s3resume = 0;
32  
33  	/* Do some early chipset init, necessary for RAM init to work */
34  	i82801gx_early_init();
35  	pineview_early_init();
36  
37  	post_code(0x30);
38  
39  	s3resume = southbridge_detect_s3_resume();
40  
41  	if (s3resume) {
42  		boot_path = BOOT_PATH_RESUME;
43  	} else {
44  		if (mchbar_read32(PMSTS) & (1 << 8)) /* HOT RESET */
45  			boot_path = BOOT_PATH_RESET;
46  		else
47  			boot_path = BOOT_PATH_NORMAL;
48  	}
49  
50  	get_mb_spd_addrmap(&spd_addrmap[0]);
51  
52  	printk(BIOS_DEBUG, "Initializing memory\n");
53  	timestamp_add_now(TS_INITRAM_START);
54  	sdram_initialize(boot_path, spd_addrmap);
55  	timestamp_add_now(TS_INITRAM_END);
56  	printk(BIOS_DEBUG, "Memory initialized\n");
57  
58  	post_code(0x31);
59  
60  	mb_pirq_setup();
61  
62  	rcba_config();
63  
64  	cbmem_was_initted = !cbmem_recovery(s3resume);
65  
66  	if (!cbmem_was_initted && s3resume) {
67  		/* Failed S3 resume, reset to come up cleanly */
68  		system_reset();
69  	}
70  
71  	romstage_handoff_init(s3resume);
72  }