proc_pio.h
1 /** 2 * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : PROC_PIO 8 // Version : 1 9 // Bus type : ahbl 10 // Description : Programmable IO block 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_PROC_PIO_DEFINED 13 #define HARDWARE_REGS_PROC_PIO_DEFINED 14 // ============================================================================= 15 // Register : PROC_PIO_CTRL 16 // Description : PIO control register 17 #define PROC_PIO_CTRL_OFFSET _u(0x00000000) 18 #define PROC_PIO_CTRL_BITS _u(0x00000fff) 19 #define PROC_PIO_CTRL_RESET _u(0x00000000) 20 #define PROC_PIO_CTRL_WIDTH _u(32) 21 // ----------------------------------------------------------------------------- 22 // Field : PROC_PIO_CTRL_CLKDIV_RESTART 23 // Description : Force clock dividers to restart their count and clear 24 // fractional 25 // accumulators. Restart multiple dividers to synchronise them. 26 #define PROC_PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) 27 #define PROC_PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) 28 #define PROC_PIO_CTRL_CLKDIV_RESTART_MSB _u(11) 29 #define PROC_PIO_CTRL_CLKDIV_RESTART_LSB _u(8) 30 #define PROC_PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" 31 // ----------------------------------------------------------------------------- 32 // Field : PROC_PIO_CTRL_SM_RESTART 33 // Description : Clear internal SM state which is otherwise difficult to access 34 // (e.g. shift counters). Self-clearing. 35 #define PROC_PIO_CTRL_SM_RESTART_RESET _u(0x0) 36 #define PROC_PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) 37 #define PROC_PIO_CTRL_SM_RESTART_MSB _u(7) 38 #define PROC_PIO_CTRL_SM_RESTART_LSB _u(4) 39 #define PROC_PIO_CTRL_SM_RESTART_ACCESS "SC" 40 // ----------------------------------------------------------------------------- 41 // Field : PROC_PIO_CTRL_SM_ENABLE 42 // Description : Enable state machine 43 #define PROC_PIO_CTRL_SM_ENABLE_RESET _u(0x0) 44 #define PROC_PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) 45 #define PROC_PIO_CTRL_SM_ENABLE_MSB _u(3) 46 #define PROC_PIO_CTRL_SM_ENABLE_LSB _u(0) 47 #define PROC_PIO_CTRL_SM_ENABLE_ACCESS "RW" 48 // ============================================================================= 49 // Register : PROC_PIO_FSTAT 50 // Description : FIFO status register 51 #define PROC_PIO_FSTAT_OFFSET _u(0x00000004) 52 #define PROC_PIO_FSTAT_BITS _u(0x0f0f0f0f) 53 #define PROC_PIO_FSTAT_RESET _u(0x0f000f00) 54 #define PROC_PIO_FSTAT_WIDTH _u(32) 55 // ----------------------------------------------------------------------------- 56 // Field : PROC_PIO_FSTAT_TXEMPTY 57 // Description : State machine TX FIFO is empty 58 #define PROC_PIO_FSTAT_TXEMPTY_RESET _u(0xf) 59 #define PROC_PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) 60 #define PROC_PIO_FSTAT_TXEMPTY_MSB _u(27) 61 #define PROC_PIO_FSTAT_TXEMPTY_LSB _u(24) 62 #define PROC_PIO_FSTAT_TXEMPTY_ACCESS "RO" 63 // ----------------------------------------------------------------------------- 64 // Field : PROC_PIO_FSTAT_TXFULL 65 // Description : State machine TX FIFO is full 66 #define PROC_PIO_FSTAT_TXFULL_RESET _u(0x0) 67 #define PROC_PIO_FSTAT_TXFULL_BITS _u(0x000f0000) 68 #define PROC_PIO_FSTAT_TXFULL_MSB _u(19) 69 #define PROC_PIO_FSTAT_TXFULL_LSB _u(16) 70 #define PROC_PIO_FSTAT_TXFULL_ACCESS "RO" 71 // ----------------------------------------------------------------------------- 72 // Field : PROC_PIO_FSTAT_RXEMPTY 73 // Description : State machine RX FIFO is empty 74 #define PROC_PIO_FSTAT_RXEMPTY_RESET _u(0xf) 75 #define PROC_PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) 76 #define PROC_PIO_FSTAT_RXEMPTY_MSB _u(11) 77 #define PROC_PIO_FSTAT_RXEMPTY_LSB _u(8) 78 #define PROC_PIO_FSTAT_RXEMPTY_ACCESS "RO" 79 // ----------------------------------------------------------------------------- 80 // Field : PROC_PIO_FSTAT_RXFULL 81 // Description : State machine RX FIFO is full 82 #define PROC_PIO_FSTAT_RXFULL_RESET _u(0x0) 83 #define PROC_PIO_FSTAT_RXFULL_BITS _u(0x0000000f) 84 #define PROC_PIO_FSTAT_RXFULL_MSB _u(3) 85 #define PROC_PIO_FSTAT_RXFULL_LSB _u(0) 86 #define PROC_PIO_FSTAT_RXFULL_ACCESS "RO" 87 // ============================================================================= 88 // Register : PROC_PIO_FDEBUG 89 // Description : FIFO debug register 90 #define PROC_PIO_FDEBUG_OFFSET _u(0x00000008) 91 #define PROC_PIO_FDEBUG_BITS _u(0x0f0f0f0f) 92 #define PROC_PIO_FDEBUG_RESET _u(0x00000000) 93 #define PROC_PIO_FDEBUG_WIDTH _u(32) 94 // ----------------------------------------------------------------------------- 95 // Field : PROC_PIO_FDEBUG_TXSTALL 96 // Description : State machine has stalled on empty TX FIFO. Write 1 to clear. 97 #define PROC_PIO_FDEBUG_TXSTALL_RESET _u(0x0) 98 #define PROC_PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) 99 #define PROC_PIO_FDEBUG_TXSTALL_MSB _u(27) 100 #define PROC_PIO_FDEBUG_TXSTALL_LSB _u(24) 101 #define PROC_PIO_FDEBUG_TXSTALL_ACCESS "WC" 102 // ----------------------------------------------------------------------------- 103 // Field : PROC_PIO_FDEBUG_TXOVER 104 // Description : TX FIFO overflow has occurred. Write 1 to clear. 105 #define PROC_PIO_FDEBUG_TXOVER_RESET _u(0x0) 106 #define PROC_PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) 107 #define PROC_PIO_FDEBUG_TXOVER_MSB _u(19) 108 #define PROC_PIO_FDEBUG_TXOVER_LSB _u(16) 109 #define PROC_PIO_FDEBUG_TXOVER_ACCESS "WC" 110 // ----------------------------------------------------------------------------- 111 // Field : PROC_PIO_FDEBUG_RXUNDER 112 // Description : RX FIFO underflow has occurred. Write 1 to clear. 113 #define PROC_PIO_FDEBUG_RXUNDER_RESET _u(0x0) 114 #define PROC_PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) 115 #define PROC_PIO_FDEBUG_RXUNDER_MSB _u(11) 116 #define PROC_PIO_FDEBUG_RXUNDER_LSB _u(8) 117 #define PROC_PIO_FDEBUG_RXUNDER_ACCESS "WC" 118 // ----------------------------------------------------------------------------- 119 // Field : PROC_PIO_FDEBUG_RXSTALL 120 // Description : State machine has stalled on full RX FIFO. Write 1 to clear. 121 #define PROC_PIO_FDEBUG_RXSTALL_RESET _u(0x0) 122 #define PROC_PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) 123 #define PROC_PIO_FDEBUG_RXSTALL_MSB _u(3) 124 #define PROC_PIO_FDEBUG_RXSTALL_LSB _u(0) 125 #define PROC_PIO_FDEBUG_RXSTALL_ACCESS "WC" 126 // ============================================================================= 127 // Register : PROC_PIO_FLEVEL 128 // Description : FIFO levels 129 // These count up to 15 only. When counting higher the extra bit 130 // is set in flevel2 register and this value saturates 131 #define PROC_PIO_FLEVEL_OFFSET _u(0x0000000c) 132 #define PROC_PIO_FLEVEL_BITS _u(0xffffffff) 133 #define PROC_PIO_FLEVEL_RESET _u(0x00000000) 134 #define PROC_PIO_FLEVEL_WIDTH _u(32) 135 // ----------------------------------------------------------------------------- 136 // Field : PROC_PIO_FLEVEL_RX3 137 // Description : None 138 #define PROC_PIO_FLEVEL_RX3_RESET _u(0x0) 139 #define PROC_PIO_FLEVEL_RX3_BITS _u(0xf0000000) 140 #define PROC_PIO_FLEVEL_RX3_MSB _u(31) 141 #define PROC_PIO_FLEVEL_RX3_LSB _u(28) 142 #define PROC_PIO_FLEVEL_RX3_ACCESS "RO" 143 // ----------------------------------------------------------------------------- 144 // Field : PROC_PIO_FLEVEL_TX3 145 // Description : None 146 #define PROC_PIO_FLEVEL_TX3_RESET _u(0x0) 147 #define PROC_PIO_FLEVEL_TX3_BITS _u(0x0f000000) 148 #define PROC_PIO_FLEVEL_TX3_MSB _u(27) 149 #define PROC_PIO_FLEVEL_TX3_LSB _u(24) 150 #define PROC_PIO_FLEVEL_TX3_ACCESS "RO" 151 // ----------------------------------------------------------------------------- 152 // Field : PROC_PIO_FLEVEL_RX2 153 // Description : None 154 #define PROC_PIO_FLEVEL_RX2_RESET _u(0x0) 155 #define PROC_PIO_FLEVEL_RX2_BITS _u(0x00f00000) 156 #define PROC_PIO_FLEVEL_RX2_MSB _u(23) 157 #define PROC_PIO_FLEVEL_RX2_LSB _u(20) 158 #define PROC_PIO_FLEVEL_RX2_ACCESS "RO" 159 // ----------------------------------------------------------------------------- 160 // Field : PROC_PIO_FLEVEL_TX2 161 // Description : None 162 #define PROC_PIO_FLEVEL_TX2_RESET _u(0x0) 163 #define PROC_PIO_FLEVEL_TX2_BITS _u(0x000f0000) 164 #define PROC_PIO_FLEVEL_TX2_MSB _u(19) 165 #define PROC_PIO_FLEVEL_TX2_LSB _u(16) 166 #define PROC_PIO_FLEVEL_TX2_ACCESS "RO" 167 // ----------------------------------------------------------------------------- 168 // Field : PROC_PIO_FLEVEL_RX1 169 // Description : None 170 #define PROC_PIO_FLEVEL_RX1_RESET _u(0x0) 171 #define PROC_PIO_FLEVEL_RX1_BITS _u(0x0000f000) 172 #define PROC_PIO_FLEVEL_RX1_MSB _u(15) 173 #define PROC_PIO_FLEVEL_RX1_LSB _u(12) 174 #define PROC_PIO_FLEVEL_RX1_ACCESS "RO" 175 // ----------------------------------------------------------------------------- 176 // Field : PROC_PIO_FLEVEL_TX1 177 // Description : None 178 #define PROC_PIO_FLEVEL_TX1_RESET _u(0x0) 179 #define PROC_PIO_FLEVEL_TX1_BITS _u(0x00000f00) 180 #define PROC_PIO_FLEVEL_TX1_MSB _u(11) 181 #define PROC_PIO_FLEVEL_TX1_LSB _u(8) 182 #define PROC_PIO_FLEVEL_TX1_ACCESS "RO" 183 // ----------------------------------------------------------------------------- 184 // Field : PROC_PIO_FLEVEL_RX0 185 // Description : None 186 #define PROC_PIO_FLEVEL_RX0_RESET _u(0x0) 187 #define PROC_PIO_FLEVEL_RX0_BITS _u(0x000000f0) 188 #define PROC_PIO_FLEVEL_RX0_MSB _u(7) 189 #define PROC_PIO_FLEVEL_RX0_LSB _u(4) 190 #define PROC_PIO_FLEVEL_RX0_ACCESS "RO" 191 // ----------------------------------------------------------------------------- 192 // Field : PROC_PIO_FLEVEL_TX0 193 // Description : None 194 #define PROC_PIO_FLEVEL_TX0_RESET _u(0x0) 195 #define PROC_PIO_FLEVEL_TX0_BITS _u(0x0000000f) 196 #define PROC_PIO_FLEVEL_TX0_MSB _u(3) 197 #define PROC_PIO_FLEVEL_TX0_LSB _u(0) 198 #define PROC_PIO_FLEVEL_TX0_ACCESS "RO" 199 // ============================================================================= 200 // Register : PROC_PIO_FLEVEL2 201 // Description : FIFO level extra bits 202 // These are only used in double fifo mode, and the fifo has more 203 // than 15 elements 204 #define PROC_PIO_FLEVEL2_OFFSET _u(0x00000010) 205 #define PROC_PIO_FLEVEL2_BITS _u(0x11111111) 206 #define PROC_PIO_FLEVEL2_RESET _u(0x00000000) 207 #define PROC_PIO_FLEVEL2_WIDTH _u(32) 208 // ----------------------------------------------------------------------------- 209 // Field : PROC_PIO_FLEVEL2_RX3 210 // Description : None 211 #define PROC_PIO_FLEVEL2_RX3_RESET _u(0x0) 212 #define PROC_PIO_FLEVEL2_RX3_BITS _u(0x10000000) 213 #define PROC_PIO_FLEVEL2_RX3_MSB _u(28) 214 #define PROC_PIO_FLEVEL2_RX3_LSB _u(28) 215 #define PROC_PIO_FLEVEL2_RX3_ACCESS "RO" 216 // ----------------------------------------------------------------------------- 217 // Field : PROC_PIO_FLEVEL2_TX3 218 // Description : None 219 #define PROC_PIO_FLEVEL2_TX3_RESET _u(0x0) 220 #define PROC_PIO_FLEVEL2_TX3_BITS _u(0x01000000) 221 #define PROC_PIO_FLEVEL2_TX3_MSB _u(24) 222 #define PROC_PIO_FLEVEL2_TX3_LSB _u(24) 223 #define PROC_PIO_FLEVEL2_TX3_ACCESS "RO" 224 // ----------------------------------------------------------------------------- 225 // Field : PROC_PIO_FLEVEL2_RX2 226 // Description : None 227 #define PROC_PIO_FLEVEL2_RX2_RESET _u(0x0) 228 #define PROC_PIO_FLEVEL2_RX2_BITS _u(0x00100000) 229 #define PROC_PIO_FLEVEL2_RX2_MSB _u(20) 230 #define PROC_PIO_FLEVEL2_RX2_LSB _u(20) 231 #define PROC_PIO_FLEVEL2_RX2_ACCESS "RO" 232 // ----------------------------------------------------------------------------- 233 // Field : PROC_PIO_FLEVEL2_TX2 234 // Description : None 235 #define PROC_PIO_FLEVEL2_TX2_RESET _u(0x0) 236 #define PROC_PIO_FLEVEL2_TX2_BITS _u(0x00010000) 237 #define PROC_PIO_FLEVEL2_TX2_MSB _u(16) 238 #define PROC_PIO_FLEVEL2_TX2_LSB _u(16) 239 #define PROC_PIO_FLEVEL2_TX2_ACCESS "RO" 240 // ----------------------------------------------------------------------------- 241 // Field : PROC_PIO_FLEVEL2_RX1 242 // Description : None 243 #define PROC_PIO_FLEVEL2_RX1_RESET _u(0x0) 244 #define PROC_PIO_FLEVEL2_RX1_BITS _u(0x00001000) 245 #define PROC_PIO_FLEVEL2_RX1_MSB _u(12) 246 #define PROC_PIO_FLEVEL2_RX1_LSB _u(12) 247 #define PROC_PIO_FLEVEL2_RX1_ACCESS "RO" 248 // ----------------------------------------------------------------------------- 249 // Field : PROC_PIO_FLEVEL2_TX1 250 // Description : None 251 #define PROC_PIO_FLEVEL2_TX1_RESET _u(0x0) 252 #define PROC_PIO_FLEVEL2_TX1_BITS _u(0x00000100) 253 #define PROC_PIO_FLEVEL2_TX1_MSB _u(8) 254 #define PROC_PIO_FLEVEL2_TX1_LSB _u(8) 255 #define PROC_PIO_FLEVEL2_TX1_ACCESS "RO" 256 // ----------------------------------------------------------------------------- 257 // Field : PROC_PIO_FLEVEL2_RX0 258 // Description : None 259 #define PROC_PIO_FLEVEL2_RX0_RESET _u(0x0) 260 #define PROC_PIO_FLEVEL2_RX0_BITS _u(0x00000010) 261 #define PROC_PIO_FLEVEL2_RX0_MSB _u(4) 262 #define PROC_PIO_FLEVEL2_RX0_LSB _u(4) 263 #define PROC_PIO_FLEVEL2_RX0_ACCESS "RO" 264 // ----------------------------------------------------------------------------- 265 // Field : PROC_PIO_FLEVEL2_TX0 266 // Description : None 267 #define PROC_PIO_FLEVEL2_TX0_RESET _u(0x0) 268 #define PROC_PIO_FLEVEL2_TX0_BITS _u(0x00000001) 269 #define PROC_PIO_FLEVEL2_TX0_MSB _u(0) 270 #define PROC_PIO_FLEVEL2_TX0_LSB _u(0) 271 #define PROC_PIO_FLEVEL2_TX0_ACCESS "RO" 272 // ============================================================================= 273 // Register : PROC_PIO_TXF0 274 // Description : Direct write access to the TX FIFO for this state machine. Each 275 // write pushes one word to the FIFO. 276 #define PROC_PIO_TXF0_OFFSET _u(0x00000014) 277 #define PROC_PIO_TXF0_BITS _u(0xffffffff) 278 #define PROC_PIO_TXF0_RESET _u(0x00000000) 279 #define PROC_PIO_TXF0_WIDTH _u(32) 280 #define PROC_PIO_TXF0_MSB _u(31) 281 #define PROC_PIO_TXF0_LSB _u(0) 282 #define PROC_PIO_TXF0_ACCESS "WF" 283 // ============================================================================= 284 // Register : PROC_PIO_TXF1 285 // Description : Direct write access to the TX FIFO for this state machine. Each 286 // write pushes one word to the FIFO. 287 #define PROC_PIO_TXF1_OFFSET _u(0x00000018) 288 #define PROC_PIO_TXF1_BITS _u(0xffffffff) 289 #define PROC_PIO_TXF1_RESET _u(0x00000000) 290 #define PROC_PIO_TXF1_WIDTH _u(32) 291 #define PROC_PIO_TXF1_MSB _u(31) 292 #define PROC_PIO_TXF1_LSB _u(0) 293 #define PROC_PIO_TXF1_ACCESS "WF" 294 // ============================================================================= 295 // Register : PROC_PIO_TXF2 296 // Description : Direct write access to the TX FIFO for this state machine. Each 297 // write pushes one word to the FIFO. 298 #define PROC_PIO_TXF2_OFFSET _u(0x0000001c) 299 #define PROC_PIO_TXF2_BITS _u(0xffffffff) 300 #define PROC_PIO_TXF2_RESET _u(0x00000000) 301 #define PROC_PIO_TXF2_WIDTH _u(32) 302 #define PROC_PIO_TXF2_MSB _u(31) 303 #define PROC_PIO_TXF2_LSB _u(0) 304 #define PROC_PIO_TXF2_ACCESS "WF" 305 // ============================================================================= 306 // Register : PROC_PIO_TXF3 307 // Description : Direct write access to the TX FIFO for this state machine. Each 308 // write pushes one word to the FIFO. 309 #define PROC_PIO_TXF3_OFFSET _u(0x00000020) 310 #define PROC_PIO_TXF3_BITS _u(0xffffffff) 311 #define PROC_PIO_TXF3_RESET _u(0x00000000) 312 #define PROC_PIO_TXF3_WIDTH _u(32) 313 #define PROC_PIO_TXF3_MSB _u(31) 314 #define PROC_PIO_TXF3_LSB _u(0) 315 #define PROC_PIO_TXF3_ACCESS "WF" 316 // ============================================================================= 317 // Register : PROC_PIO_RXF0 318 // Description : Direct read access to the RX FIFO for this state machine. Each 319 // read pops one word from the FIFO. 320 #define PROC_PIO_RXF0_OFFSET _u(0x00000024) 321 #define PROC_PIO_RXF0_BITS _u(0xffffffff) 322 #define PROC_PIO_RXF0_RESET "-" 323 #define PROC_PIO_RXF0_WIDTH _u(32) 324 #define PROC_PIO_RXF0_MSB _u(31) 325 #define PROC_PIO_RXF0_LSB _u(0) 326 #define PROC_PIO_RXF0_ACCESS "RF" 327 // ============================================================================= 328 // Register : PROC_PIO_RXF1 329 // Description : Direct read access to the RX FIFO for this state machine. Each 330 // read pops one word from the FIFO. 331 #define PROC_PIO_RXF1_OFFSET _u(0x00000028) 332 #define PROC_PIO_RXF1_BITS _u(0xffffffff) 333 #define PROC_PIO_RXF1_RESET "-" 334 #define PROC_PIO_RXF1_WIDTH _u(32) 335 #define PROC_PIO_RXF1_MSB _u(31) 336 #define PROC_PIO_RXF1_LSB _u(0) 337 #define PROC_PIO_RXF1_ACCESS "RF" 338 // ============================================================================= 339 // Register : PROC_PIO_RXF2 340 // Description : Direct read access to the RX FIFO for this state machine. Each 341 // read pops one word from the FIFO. 342 #define PROC_PIO_RXF2_OFFSET _u(0x0000002c) 343 #define PROC_PIO_RXF2_BITS _u(0xffffffff) 344 #define PROC_PIO_RXF2_RESET "-" 345 #define PROC_PIO_RXF2_WIDTH _u(32) 346 #define PROC_PIO_RXF2_MSB _u(31) 347 #define PROC_PIO_RXF2_LSB _u(0) 348 #define PROC_PIO_RXF2_ACCESS "RF" 349 // ============================================================================= 350 // Register : PROC_PIO_RXF3 351 // Description : Direct read access to the RX FIFO for this state machine. Each 352 // read pops one word from the FIFO. 353 #define PROC_PIO_RXF3_OFFSET _u(0x00000030) 354 #define PROC_PIO_RXF3_BITS _u(0xffffffff) 355 #define PROC_PIO_RXF3_RESET "-" 356 #define PROC_PIO_RXF3_WIDTH _u(32) 357 #define PROC_PIO_RXF3_MSB _u(31) 358 #define PROC_PIO_RXF3_LSB _u(0) 359 #define PROC_PIO_RXF3_ACCESS "RF" 360 // ============================================================================= 361 // Register : PROC_PIO_IRQ 362 // Description : Interrupt request register. Write 1 to clear 363 #define PROC_PIO_IRQ_OFFSET _u(0x00000034) 364 #define PROC_PIO_IRQ_BITS _u(0x000000ff) 365 #define PROC_PIO_IRQ_RESET _u(0x00000000) 366 #define PROC_PIO_IRQ_WIDTH _u(32) 367 #define PROC_PIO_IRQ_MSB _u(7) 368 #define PROC_PIO_IRQ_LSB _u(0) 369 #define PROC_PIO_IRQ_ACCESS "WC" 370 // ============================================================================= 371 // Register : PROC_PIO_IRQ_FORCE 372 // Description : Writing a 1 to each of these bits will forcibly assert the 373 // corresponding IRQ. 374 // Note this is different to the INTF register: writing here 375 // affects PIO internal 376 // state. INTF just asserts the processor-facing IRQ signal for 377 // testing ISRs, 378 // and is not visible to the state machines. 379 #define PROC_PIO_IRQ_FORCE_OFFSET _u(0x00000038) 380 #define PROC_PIO_IRQ_FORCE_BITS _u(0x000000ff) 381 #define PROC_PIO_IRQ_FORCE_RESET _u(0x00000000) 382 #define PROC_PIO_IRQ_FORCE_WIDTH _u(32) 383 #define PROC_PIO_IRQ_FORCE_MSB _u(7) 384 #define PROC_PIO_IRQ_FORCE_LSB _u(0) 385 #define PROC_PIO_IRQ_FORCE_ACCESS "WF" 386 // ============================================================================= 387 // Register : PROC_PIO_INPUT_SYNC_BYPASS 388 // Description : There is a 2-flipflop synchronizer on each GPIO input, which 389 // protects 390 // PIO logic from metastabilities. This increases input delay, and 391 // for fast 392 // synchronous IO (e.g. SPI) these synchronizers may need to be 393 // bypassed. 394 // Each bit in this register corresponds to one GPIO. 395 // 0 -> input is synchronized (default) 396 // 1 -> synchronizer is bypassed 397 // If in doubt, leave this register as all zeroes. 398 #define PROC_PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x0000003c) 399 #define PROC_PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) 400 #define PROC_PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) 401 #define PROC_PIO_INPUT_SYNC_BYPASS_WIDTH _u(32) 402 #define PROC_PIO_INPUT_SYNC_BYPASS_MSB _u(31) 403 #define PROC_PIO_INPUT_SYNC_BYPASS_LSB _u(0) 404 #define PROC_PIO_INPUT_SYNC_BYPASS_ACCESS "RW" 405 // ============================================================================= 406 // Register : PROC_PIO_DBG_PADOUT 407 // Description : Read to sample the pad output values PIO is currently driving 408 // to the GPIOs. 409 #define PROC_PIO_DBG_PADOUT_OFFSET _u(0x00000040) 410 #define PROC_PIO_DBG_PADOUT_BITS _u(0xffffffff) 411 #define PROC_PIO_DBG_PADOUT_RESET _u(0x00000000) 412 #define PROC_PIO_DBG_PADOUT_WIDTH _u(32) 413 #define PROC_PIO_DBG_PADOUT_MSB _u(31) 414 #define PROC_PIO_DBG_PADOUT_LSB _u(0) 415 #define PROC_PIO_DBG_PADOUT_ACCESS "RO" 416 // ============================================================================= 417 // Register : PROC_PIO_DBG_PADOE 418 // Description : Read to sample the pad output enables (direction) PIO is 419 // currently driving to the GPIOs. 420 #define PROC_PIO_DBG_PADOE_OFFSET _u(0x00000044) 421 #define PROC_PIO_DBG_PADOE_BITS _u(0xffffffff) 422 #define PROC_PIO_DBG_PADOE_RESET _u(0x00000000) 423 #define PROC_PIO_DBG_PADOE_WIDTH _u(32) 424 #define PROC_PIO_DBG_PADOE_MSB _u(31) 425 #define PROC_PIO_DBG_PADOE_LSB _u(0) 426 #define PROC_PIO_DBG_PADOE_ACCESS "RO" 427 // ============================================================================= 428 // Register : PROC_PIO_DBG_CFGINFO 429 // Description : The PIO hardware has some free parameters that may vary between 430 // chip products. 431 // These should be provided in the chip datasheet, but are also 432 // exposed here. 433 #define PROC_PIO_DBG_CFGINFO_OFFSET _u(0x00000048) 434 #define PROC_PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) 435 #define PROC_PIO_DBG_CFGINFO_RESET _u(0x00000000) 436 #define PROC_PIO_DBG_CFGINFO_WIDTH _u(32) 437 // ----------------------------------------------------------------------------- 438 // Field : PROC_PIO_DBG_CFGINFO_IMEM_SIZE 439 // Description : The size of the instruction memory, measured in units of one 440 // instruction 441 #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" 442 #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) 443 #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) 444 #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) 445 #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" 446 // ----------------------------------------------------------------------------- 447 // Field : PROC_PIO_DBG_CFGINFO_SM_COUNT 448 // Description : The number of state machines this PIO instance is equipped 449 // with. 450 #define PROC_PIO_DBG_CFGINFO_SM_COUNT_RESET "-" 451 #define PROC_PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) 452 #define PROC_PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) 453 #define PROC_PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) 454 #define PROC_PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" 455 // ----------------------------------------------------------------------------- 456 // Field : PROC_PIO_DBG_CFGINFO_FIFO_DEPTH 457 // Description : The depth of the state machine TX/RX FIFOs, measured in words. 458 // Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double 459 // this depth. 460 #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" 461 #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) 462 #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) 463 #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) 464 #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" 465 // ============================================================================= 466 // Register : PROC_PIO_INSTR_MEM0 467 // Description : Write-only access to instruction memory location 0 468 #define PROC_PIO_INSTR_MEM0_OFFSET _u(0x0000004c) 469 #define PROC_PIO_INSTR_MEM0_BITS _u(0x0000ffff) 470 #define PROC_PIO_INSTR_MEM0_RESET _u(0x00000000) 471 #define PROC_PIO_INSTR_MEM0_WIDTH _u(32) 472 #define PROC_PIO_INSTR_MEM0_MSB _u(15) 473 #define PROC_PIO_INSTR_MEM0_LSB _u(0) 474 #define PROC_PIO_INSTR_MEM0_ACCESS "WO" 475 // ============================================================================= 476 // Register : PROC_PIO_INSTR_MEM1 477 // Description : Write-only access to instruction memory location 1 478 #define PROC_PIO_INSTR_MEM1_OFFSET _u(0x00000050) 479 #define PROC_PIO_INSTR_MEM1_BITS _u(0x0000ffff) 480 #define PROC_PIO_INSTR_MEM1_RESET _u(0x00000000) 481 #define PROC_PIO_INSTR_MEM1_WIDTH _u(32) 482 #define PROC_PIO_INSTR_MEM1_MSB _u(15) 483 #define PROC_PIO_INSTR_MEM1_LSB _u(0) 484 #define PROC_PIO_INSTR_MEM1_ACCESS "WO" 485 // ============================================================================= 486 // Register : PROC_PIO_INSTR_MEM2 487 // Description : Write-only access to instruction memory location 2 488 #define PROC_PIO_INSTR_MEM2_OFFSET _u(0x00000054) 489 #define PROC_PIO_INSTR_MEM2_BITS _u(0x0000ffff) 490 #define PROC_PIO_INSTR_MEM2_RESET _u(0x00000000) 491 #define PROC_PIO_INSTR_MEM2_WIDTH _u(32) 492 #define PROC_PIO_INSTR_MEM2_MSB _u(15) 493 #define PROC_PIO_INSTR_MEM2_LSB _u(0) 494 #define PROC_PIO_INSTR_MEM2_ACCESS "WO" 495 // ============================================================================= 496 // Register : PROC_PIO_INSTR_MEM3 497 // Description : Write-only access to instruction memory location 3 498 #define PROC_PIO_INSTR_MEM3_OFFSET _u(0x00000058) 499 #define PROC_PIO_INSTR_MEM3_BITS _u(0x0000ffff) 500 #define PROC_PIO_INSTR_MEM3_RESET _u(0x00000000) 501 #define PROC_PIO_INSTR_MEM3_WIDTH _u(32) 502 #define PROC_PIO_INSTR_MEM3_MSB _u(15) 503 #define PROC_PIO_INSTR_MEM3_LSB _u(0) 504 #define PROC_PIO_INSTR_MEM3_ACCESS "WO" 505 // ============================================================================= 506 // Register : PROC_PIO_INSTR_MEM4 507 // Description : Write-only access to instruction memory location 4 508 #define PROC_PIO_INSTR_MEM4_OFFSET _u(0x0000005c) 509 #define PROC_PIO_INSTR_MEM4_BITS _u(0x0000ffff) 510 #define PROC_PIO_INSTR_MEM4_RESET _u(0x00000000) 511 #define PROC_PIO_INSTR_MEM4_WIDTH _u(32) 512 #define PROC_PIO_INSTR_MEM4_MSB _u(15) 513 #define PROC_PIO_INSTR_MEM4_LSB _u(0) 514 #define PROC_PIO_INSTR_MEM4_ACCESS "WO" 515 // ============================================================================= 516 // Register : PROC_PIO_INSTR_MEM5 517 // Description : Write-only access to instruction memory location 5 518 #define PROC_PIO_INSTR_MEM5_OFFSET _u(0x00000060) 519 #define PROC_PIO_INSTR_MEM5_BITS _u(0x0000ffff) 520 #define PROC_PIO_INSTR_MEM5_RESET _u(0x00000000) 521 #define PROC_PIO_INSTR_MEM5_WIDTH _u(32) 522 #define PROC_PIO_INSTR_MEM5_MSB _u(15) 523 #define PROC_PIO_INSTR_MEM5_LSB _u(0) 524 #define PROC_PIO_INSTR_MEM5_ACCESS "WO" 525 // ============================================================================= 526 // Register : PROC_PIO_INSTR_MEM6 527 // Description : Write-only access to instruction memory location 6 528 #define PROC_PIO_INSTR_MEM6_OFFSET _u(0x00000064) 529 #define PROC_PIO_INSTR_MEM6_BITS _u(0x0000ffff) 530 #define PROC_PIO_INSTR_MEM6_RESET _u(0x00000000) 531 #define PROC_PIO_INSTR_MEM6_WIDTH _u(32) 532 #define PROC_PIO_INSTR_MEM6_MSB _u(15) 533 #define PROC_PIO_INSTR_MEM6_LSB _u(0) 534 #define PROC_PIO_INSTR_MEM6_ACCESS "WO" 535 // ============================================================================= 536 // Register : PROC_PIO_INSTR_MEM7 537 // Description : Write-only access to instruction memory location 7 538 #define PROC_PIO_INSTR_MEM7_OFFSET _u(0x00000068) 539 #define PROC_PIO_INSTR_MEM7_BITS _u(0x0000ffff) 540 #define PROC_PIO_INSTR_MEM7_RESET _u(0x00000000) 541 #define PROC_PIO_INSTR_MEM7_WIDTH _u(32) 542 #define PROC_PIO_INSTR_MEM7_MSB _u(15) 543 #define PROC_PIO_INSTR_MEM7_LSB _u(0) 544 #define PROC_PIO_INSTR_MEM7_ACCESS "WO" 545 // ============================================================================= 546 // Register : PROC_PIO_INSTR_MEM8 547 // Description : Write-only access to instruction memory location 8 548 #define PROC_PIO_INSTR_MEM8_OFFSET _u(0x0000006c) 549 #define PROC_PIO_INSTR_MEM8_BITS _u(0x0000ffff) 550 #define PROC_PIO_INSTR_MEM8_RESET _u(0x00000000) 551 #define PROC_PIO_INSTR_MEM8_WIDTH _u(32) 552 #define PROC_PIO_INSTR_MEM8_MSB _u(15) 553 #define PROC_PIO_INSTR_MEM8_LSB _u(0) 554 #define PROC_PIO_INSTR_MEM8_ACCESS "WO" 555 // ============================================================================= 556 // Register : PROC_PIO_INSTR_MEM9 557 // Description : Write-only access to instruction memory location 9 558 #define PROC_PIO_INSTR_MEM9_OFFSET _u(0x00000070) 559 #define PROC_PIO_INSTR_MEM9_BITS _u(0x0000ffff) 560 #define PROC_PIO_INSTR_MEM9_RESET _u(0x00000000) 561 #define PROC_PIO_INSTR_MEM9_WIDTH _u(32) 562 #define PROC_PIO_INSTR_MEM9_MSB _u(15) 563 #define PROC_PIO_INSTR_MEM9_LSB _u(0) 564 #define PROC_PIO_INSTR_MEM9_ACCESS "WO" 565 // ============================================================================= 566 // Register : PROC_PIO_INSTR_MEM10 567 // Description : Write-only access to instruction memory location 10 568 #define PROC_PIO_INSTR_MEM10_OFFSET _u(0x00000074) 569 #define PROC_PIO_INSTR_MEM10_BITS _u(0x0000ffff) 570 #define PROC_PIO_INSTR_MEM10_RESET _u(0x00000000) 571 #define PROC_PIO_INSTR_MEM10_WIDTH _u(32) 572 #define PROC_PIO_INSTR_MEM10_MSB _u(15) 573 #define PROC_PIO_INSTR_MEM10_LSB _u(0) 574 #define PROC_PIO_INSTR_MEM10_ACCESS "WO" 575 // ============================================================================= 576 // Register : PROC_PIO_INSTR_MEM11 577 // Description : Write-only access to instruction memory location 11 578 #define PROC_PIO_INSTR_MEM11_OFFSET _u(0x00000078) 579 #define PROC_PIO_INSTR_MEM11_BITS _u(0x0000ffff) 580 #define PROC_PIO_INSTR_MEM11_RESET _u(0x00000000) 581 #define PROC_PIO_INSTR_MEM11_WIDTH _u(32) 582 #define PROC_PIO_INSTR_MEM11_MSB _u(15) 583 #define PROC_PIO_INSTR_MEM11_LSB _u(0) 584 #define PROC_PIO_INSTR_MEM11_ACCESS "WO" 585 // ============================================================================= 586 // Register : PROC_PIO_INSTR_MEM12 587 // Description : Write-only access to instruction memory location 12 588 #define PROC_PIO_INSTR_MEM12_OFFSET _u(0x0000007c) 589 #define PROC_PIO_INSTR_MEM12_BITS _u(0x0000ffff) 590 #define PROC_PIO_INSTR_MEM12_RESET _u(0x00000000) 591 #define PROC_PIO_INSTR_MEM12_WIDTH _u(32) 592 #define PROC_PIO_INSTR_MEM12_MSB _u(15) 593 #define PROC_PIO_INSTR_MEM12_LSB _u(0) 594 #define PROC_PIO_INSTR_MEM12_ACCESS "WO" 595 // ============================================================================= 596 // Register : PROC_PIO_INSTR_MEM13 597 // Description : Write-only access to instruction memory location 13 598 #define PROC_PIO_INSTR_MEM13_OFFSET _u(0x00000080) 599 #define PROC_PIO_INSTR_MEM13_BITS _u(0x0000ffff) 600 #define PROC_PIO_INSTR_MEM13_RESET _u(0x00000000) 601 #define PROC_PIO_INSTR_MEM13_WIDTH _u(32) 602 #define PROC_PIO_INSTR_MEM13_MSB _u(15) 603 #define PROC_PIO_INSTR_MEM13_LSB _u(0) 604 #define PROC_PIO_INSTR_MEM13_ACCESS "WO" 605 // ============================================================================= 606 // Register : PROC_PIO_INSTR_MEM14 607 // Description : Write-only access to instruction memory location 14 608 #define PROC_PIO_INSTR_MEM14_OFFSET _u(0x00000084) 609 #define PROC_PIO_INSTR_MEM14_BITS _u(0x0000ffff) 610 #define PROC_PIO_INSTR_MEM14_RESET _u(0x00000000) 611 #define PROC_PIO_INSTR_MEM14_WIDTH _u(32) 612 #define PROC_PIO_INSTR_MEM14_MSB _u(15) 613 #define PROC_PIO_INSTR_MEM14_LSB _u(0) 614 #define PROC_PIO_INSTR_MEM14_ACCESS "WO" 615 // ============================================================================= 616 // Register : PROC_PIO_INSTR_MEM15 617 // Description : Write-only access to instruction memory location 15 618 #define PROC_PIO_INSTR_MEM15_OFFSET _u(0x00000088) 619 #define PROC_PIO_INSTR_MEM15_BITS _u(0x0000ffff) 620 #define PROC_PIO_INSTR_MEM15_RESET _u(0x00000000) 621 #define PROC_PIO_INSTR_MEM15_WIDTH _u(32) 622 #define PROC_PIO_INSTR_MEM15_MSB _u(15) 623 #define PROC_PIO_INSTR_MEM15_LSB _u(0) 624 #define PROC_PIO_INSTR_MEM15_ACCESS "WO" 625 // ============================================================================= 626 // Register : PROC_PIO_INSTR_MEM16 627 // Description : Write-only access to instruction memory location 16 628 #define PROC_PIO_INSTR_MEM16_OFFSET _u(0x0000008c) 629 #define PROC_PIO_INSTR_MEM16_BITS _u(0x0000ffff) 630 #define PROC_PIO_INSTR_MEM16_RESET _u(0x00000000) 631 #define PROC_PIO_INSTR_MEM16_WIDTH _u(32) 632 #define PROC_PIO_INSTR_MEM16_MSB _u(15) 633 #define PROC_PIO_INSTR_MEM16_LSB _u(0) 634 #define PROC_PIO_INSTR_MEM16_ACCESS "WO" 635 // ============================================================================= 636 // Register : PROC_PIO_INSTR_MEM17 637 // Description : Write-only access to instruction memory location 17 638 #define PROC_PIO_INSTR_MEM17_OFFSET _u(0x00000090) 639 #define PROC_PIO_INSTR_MEM17_BITS _u(0x0000ffff) 640 #define PROC_PIO_INSTR_MEM17_RESET _u(0x00000000) 641 #define PROC_PIO_INSTR_MEM17_WIDTH _u(32) 642 #define PROC_PIO_INSTR_MEM17_MSB _u(15) 643 #define PROC_PIO_INSTR_MEM17_LSB _u(0) 644 #define PROC_PIO_INSTR_MEM17_ACCESS "WO" 645 // ============================================================================= 646 // Register : PROC_PIO_INSTR_MEM18 647 // Description : Write-only access to instruction memory location 18 648 #define PROC_PIO_INSTR_MEM18_OFFSET _u(0x00000094) 649 #define PROC_PIO_INSTR_MEM18_BITS _u(0x0000ffff) 650 #define PROC_PIO_INSTR_MEM18_RESET _u(0x00000000) 651 #define PROC_PIO_INSTR_MEM18_WIDTH _u(32) 652 #define PROC_PIO_INSTR_MEM18_MSB _u(15) 653 #define PROC_PIO_INSTR_MEM18_LSB _u(0) 654 #define PROC_PIO_INSTR_MEM18_ACCESS "WO" 655 // ============================================================================= 656 // Register : PROC_PIO_INSTR_MEM19 657 // Description : Write-only access to instruction memory location 19 658 #define PROC_PIO_INSTR_MEM19_OFFSET _u(0x00000098) 659 #define PROC_PIO_INSTR_MEM19_BITS _u(0x0000ffff) 660 #define PROC_PIO_INSTR_MEM19_RESET _u(0x00000000) 661 #define PROC_PIO_INSTR_MEM19_WIDTH _u(32) 662 #define PROC_PIO_INSTR_MEM19_MSB _u(15) 663 #define PROC_PIO_INSTR_MEM19_LSB _u(0) 664 #define PROC_PIO_INSTR_MEM19_ACCESS "WO" 665 // ============================================================================= 666 // Register : PROC_PIO_INSTR_MEM20 667 // Description : Write-only access to instruction memory location 20 668 #define PROC_PIO_INSTR_MEM20_OFFSET _u(0x0000009c) 669 #define PROC_PIO_INSTR_MEM20_BITS _u(0x0000ffff) 670 #define PROC_PIO_INSTR_MEM20_RESET _u(0x00000000) 671 #define PROC_PIO_INSTR_MEM20_WIDTH _u(32) 672 #define PROC_PIO_INSTR_MEM20_MSB _u(15) 673 #define PROC_PIO_INSTR_MEM20_LSB _u(0) 674 #define PROC_PIO_INSTR_MEM20_ACCESS "WO" 675 // ============================================================================= 676 // Register : PROC_PIO_INSTR_MEM21 677 // Description : Write-only access to instruction memory location 21 678 #define PROC_PIO_INSTR_MEM21_OFFSET _u(0x000000a0) 679 #define PROC_PIO_INSTR_MEM21_BITS _u(0x0000ffff) 680 #define PROC_PIO_INSTR_MEM21_RESET _u(0x00000000) 681 #define PROC_PIO_INSTR_MEM21_WIDTH _u(32) 682 #define PROC_PIO_INSTR_MEM21_MSB _u(15) 683 #define PROC_PIO_INSTR_MEM21_LSB _u(0) 684 #define PROC_PIO_INSTR_MEM21_ACCESS "WO" 685 // ============================================================================= 686 // Register : PROC_PIO_INSTR_MEM22 687 // Description : Write-only access to instruction memory location 22 688 #define PROC_PIO_INSTR_MEM22_OFFSET _u(0x000000a4) 689 #define PROC_PIO_INSTR_MEM22_BITS _u(0x0000ffff) 690 #define PROC_PIO_INSTR_MEM22_RESET _u(0x00000000) 691 #define PROC_PIO_INSTR_MEM22_WIDTH _u(32) 692 #define PROC_PIO_INSTR_MEM22_MSB _u(15) 693 #define PROC_PIO_INSTR_MEM22_LSB _u(0) 694 #define PROC_PIO_INSTR_MEM22_ACCESS "WO" 695 // ============================================================================= 696 // Register : PROC_PIO_INSTR_MEM23 697 // Description : Write-only access to instruction memory location 23 698 #define PROC_PIO_INSTR_MEM23_OFFSET _u(0x000000a8) 699 #define PROC_PIO_INSTR_MEM23_BITS _u(0x0000ffff) 700 #define PROC_PIO_INSTR_MEM23_RESET _u(0x00000000) 701 #define PROC_PIO_INSTR_MEM23_WIDTH _u(32) 702 #define PROC_PIO_INSTR_MEM23_MSB _u(15) 703 #define PROC_PIO_INSTR_MEM23_LSB _u(0) 704 #define PROC_PIO_INSTR_MEM23_ACCESS "WO" 705 // ============================================================================= 706 // Register : PROC_PIO_INSTR_MEM24 707 // Description : Write-only access to instruction memory location 24 708 #define PROC_PIO_INSTR_MEM24_OFFSET _u(0x000000ac) 709 #define PROC_PIO_INSTR_MEM24_BITS _u(0x0000ffff) 710 #define PROC_PIO_INSTR_MEM24_RESET _u(0x00000000) 711 #define PROC_PIO_INSTR_MEM24_WIDTH _u(32) 712 #define PROC_PIO_INSTR_MEM24_MSB _u(15) 713 #define PROC_PIO_INSTR_MEM24_LSB _u(0) 714 #define PROC_PIO_INSTR_MEM24_ACCESS "WO" 715 // ============================================================================= 716 // Register : PROC_PIO_INSTR_MEM25 717 // Description : Write-only access to instruction memory location 25 718 #define PROC_PIO_INSTR_MEM25_OFFSET _u(0x000000b0) 719 #define PROC_PIO_INSTR_MEM25_BITS _u(0x0000ffff) 720 #define PROC_PIO_INSTR_MEM25_RESET _u(0x00000000) 721 #define PROC_PIO_INSTR_MEM25_WIDTH _u(32) 722 #define PROC_PIO_INSTR_MEM25_MSB _u(15) 723 #define PROC_PIO_INSTR_MEM25_LSB _u(0) 724 #define PROC_PIO_INSTR_MEM25_ACCESS "WO" 725 // ============================================================================= 726 // Register : PROC_PIO_INSTR_MEM26 727 // Description : Write-only access to instruction memory location 26 728 #define PROC_PIO_INSTR_MEM26_OFFSET _u(0x000000b4) 729 #define PROC_PIO_INSTR_MEM26_BITS _u(0x0000ffff) 730 #define PROC_PIO_INSTR_MEM26_RESET _u(0x00000000) 731 #define PROC_PIO_INSTR_MEM26_WIDTH _u(32) 732 #define PROC_PIO_INSTR_MEM26_MSB _u(15) 733 #define PROC_PIO_INSTR_MEM26_LSB _u(0) 734 #define PROC_PIO_INSTR_MEM26_ACCESS "WO" 735 // ============================================================================= 736 // Register : PROC_PIO_INSTR_MEM27 737 // Description : Write-only access to instruction memory location 27 738 #define PROC_PIO_INSTR_MEM27_OFFSET _u(0x000000b8) 739 #define PROC_PIO_INSTR_MEM27_BITS _u(0x0000ffff) 740 #define PROC_PIO_INSTR_MEM27_RESET _u(0x00000000) 741 #define PROC_PIO_INSTR_MEM27_WIDTH _u(32) 742 #define PROC_PIO_INSTR_MEM27_MSB _u(15) 743 #define PROC_PIO_INSTR_MEM27_LSB _u(0) 744 #define PROC_PIO_INSTR_MEM27_ACCESS "WO" 745 // ============================================================================= 746 // Register : PROC_PIO_INSTR_MEM28 747 // Description : Write-only access to instruction memory location 28 748 #define PROC_PIO_INSTR_MEM28_OFFSET _u(0x000000bc) 749 #define PROC_PIO_INSTR_MEM28_BITS _u(0x0000ffff) 750 #define PROC_PIO_INSTR_MEM28_RESET _u(0x00000000) 751 #define PROC_PIO_INSTR_MEM28_WIDTH _u(32) 752 #define PROC_PIO_INSTR_MEM28_MSB _u(15) 753 #define PROC_PIO_INSTR_MEM28_LSB _u(0) 754 #define PROC_PIO_INSTR_MEM28_ACCESS "WO" 755 // ============================================================================= 756 // Register : PROC_PIO_INSTR_MEM29 757 // Description : Write-only access to instruction memory location 29 758 #define PROC_PIO_INSTR_MEM29_OFFSET _u(0x000000c0) 759 #define PROC_PIO_INSTR_MEM29_BITS _u(0x0000ffff) 760 #define PROC_PIO_INSTR_MEM29_RESET _u(0x00000000) 761 #define PROC_PIO_INSTR_MEM29_WIDTH _u(32) 762 #define PROC_PIO_INSTR_MEM29_MSB _u(15) 763 #define PROC_PIO_INSTR_MEM29_LSB _u(0) 764 #define PROC_PIO_INSTR_MEM29_ACCESS "WO" 765 // ============================================================================= 766 // Register : PROC_PIO_INSTR_MEM30 767 // Description : Write-only access to instruction memory location 30 768 #define PROC_PIO_INSTR_MEM30_OFFSET _u(0x000000c4) 769 #define PROC_PIO_INSTR_MEM30_BITS _u(0x0000ffff) 770 #define PROC_PIO_INSTR_MEM30_RESET _u(0x00000000) 771 #define PROC_PIO_INSTR_MEM30_WIDTH _u(32) 772 #define PROC_PIO_INSTR_MEM30_MSB _u(15) 773 #define PROC_PIO_INSTR_MEM30_LSB _u(0) 774 #define PROC_PIO_INSTR_MEM30_ACCESS "WO" 775 // ============================================================================= 776 // Register : PROC_PIO_INSTR_MEM31 777 // Description : Write-only access to instruction memory location 31 778 #define PROC_PIO_INSTR_MEM31_OFFSET _u(0x000000c8) 779 #define PROC_PIO_INSTR_MEM31_BITS _u(0x0000ffff) 780 #define PROC_PIO_INSTR_MEM31_RESET _u(0x00000000) 781 #define PROC_PIO_INSTR_MEM31_WIDTH _u(32) 782 #define PROC_PIO_INSTR_MEM31_MSB _u(15) 783 #define PROC_PIO_INSTR_MEM31_LSB _u(0) 784 #define PROC_PIO_INSTR_MEM31_ACCESS "WO" 785 // ============================================================================= 786 // Register : PROC_PIO_SM0_CLKDIV 787 // Description : Clock divider register for state machine 0 788 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 789 #define PROC_PIO_SM0_CLKDIV_OFFSET _u(0x000000cc) 790 #define PROC_PIO_SM0_CLKDIV_BITS _u(0xffffff00) 791 #define PROC_PIO_SM0_CLKDIV_RESET _u(0x00010000) 792 #define PROC_PIO_SM0_CLKDIV_WIDTH _u(32) 793 // ----------------------------------------------------------------------------- 794 // Field : PROC_PIO_SM0_CLKDIV_INT 795 // Description : Effective frequency is sysclk/int. 796 // Value of 0 is interpreted as max possible value 797 #define PROC_PIO_SM0_CLKDIV_INT_RESET _u(0x0001) 798 #define PROC_PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) 799 #define PROC_PIO_SM0_CLKDIV_INT_MSB _u(31) 800 #define PROC_PIO_SM0_CLKDIV_INT_LSB _u(16) 801 #define PROC_PIO_SM0_CLKDIV_INT_ACCESS "RW" 802 // ----------------------------------------------------------------------------- 803 // Field : PROC_PIO_SM0_CLKDIV_FRAC 804 // Description : Fractional part of clock divider 805 #define PROC_PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) 806 #define PROC_PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) 807 #define PROC_PIO_SM0_CLKDIV_FRAC_MSB _u(15) 808 #define PROC_PIO_SM0_CLKDIV_FRAC_LSB _u(8) 809 #define PROC_PIO_SM0_CLKDIV_FRAC_ACCESS "RW" 810 // ============================================================================= 811 // Register : PROC_PIO_SM0_EXECCTRL 812 // Description : Execution/behavioural settings for state machine 0 813 #define PROC_PIO_SM0_EXECCTRL_OFFSET _u(0x000000d0) 814 #define PROC_PIO_SM0_EXECCTRL_BITS _u(0xffffffbf) 815 #define PROC_PIO_SM0_EXECCTRL_RESET _u(0x0001f000) 816 #define PROC_PIO_SM0_EXECCTRL_WIDTH _u(32) 817 // ----------------------------------------------------------------------------- 818 // Field : PROC_PIO_SM0_EXECCTRL_EXEC_STALLED 819 // Description : An instruction written to SMx_INSTR is stalled, and latched by 820 // the 821 // state machine. Will clear once the instruction completes. 822 #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) 823 #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) 824 #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) 825 #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) 826 #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" 827 // ----------------------------------------------------------------------------- 828 // Field : PROC_PIO_SM0_EXECCTRL_SIDE_EN 829 // Description : If 1, the delay MSB is used as side-set enable, rather than a 830 // side-set data bit. This allows instructions to perform side-set 831 // optionally, 832 // rather than on every instruction. 833 #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) 834 #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) 835 #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) 836 #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) 837 #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" 838 // ----------------------------------------------------------------------------- 839 // Field : PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR 840 // Description : Side-set data is asserted to pin OEs instead of pin values 841 #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) 842 #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) 843 #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) 844 #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) 845 #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 846 // ----------------------------------------------------------------------------- 847 // Field : PROC_PIO_SM0_EXECCTRL_JMP_PIN 848 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 849 // input mapping. 850 #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) 851 #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) 852 #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) 853 #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) 854 #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" 855 // ----------------------------------------------------------------------------- 856 // Field : PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL 857 // Description : Which data bit to use for inline OUT enable 858 #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) 859 #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) 860 #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) 861 #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) 862 #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 863 // ----------------------------------------------------------------------------- 864 // Field : PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN 865 // Description : If 1, use a bit of OUT data as an auxiliary write enable 866 // When used in conjunction with OUT_STICKY, writes with an enable 867 // of 0 will 868 // deassert the latest pin write. This can create useful 869 // masking/override behaviour 870 // due to the priority ordering of state machine pin writes (SM0 < 871 // SM1 < ...) 872 #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) 873 #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) 874 #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) 875 #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) 876 #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 877 // ----------------------------------------------------------------------------- 878 // Field : PROC_PIO_SM0_EXECCTRL_OUT_STICKY 879 // Description : Continuously assert the most recent OUT/SET to the pins 880 #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) 881 #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) 882 #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) 883 #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) 884 #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" 885 // ----------------------------------------------------------------------------- 886 // Field : PROC_PIO_SM0_EXECCTRL_WRAP_TOP 887 // Description : After reaching this address, execution is wrapped to 888 // wrap_bottom. 889 // If the instruction is a jump, and the jump condition is true, 890 // the jump takes priority. 891 #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) 892 #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) 893 #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) 894 #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) 895 #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" 896 // ----------------------------------------------------------------------------- 897 // Field : PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM 898 // Description : After reaching wrap_top, execution is wrapped to this address. 899 #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) 900 #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) 901 #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) 902 #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) 903 #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 904 // ----------------------------------------------------------------------------- 905 // Field : PROC_PIO_SM0_EXECCTRL_STATUS_SEL 906 // Description : Comparison used for the MOV x, STATUS instruction. 907 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 908 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 909 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) 910 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) 911 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(5) 912 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) 913 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" 914 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) 915 #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) 916 // ----------------------------------------------------------------------------- 917 // Field : PROC_PIO_SM0_EXECCTRL_STATUS_N 918 // Description : Comparison level for the MOV x, STATUS instruction 919 #define PROC_PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) 920 #define PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) 921 #define PROC_PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) 922 #define PROC_PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) 923 #define PROC_PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" 924 // ============================================================================= 925 // Register : PROC_PIO_SM0_SHIFTCTRL 926 // Description : Control behaviour of the input/output shift registers for state 927 // machine 0 928 #define PROC_PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d4) 929 #define PROC_PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) 930 #define PROC_PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) 931 #define PROC_PIO_SM0_SHIFTCTRL_WIDTH _u(32) 932 // ----------------------------------------------------------------------------- 933 // Field : PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX 934 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 935 // as deep. 936 // TX FIFO is disabled as a result (always reads as both full and 937 // empty). 938 // FIFOs are flushed when this bit is changed. 939 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) 940 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) 941 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) 942 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) 943 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 944 // ----------------------------------------------------------------------------- 945 // Field : PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX 946 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 947 // as deep. 948 // RX FIFO is disabled as a result (always reads as both full and 949 // empty). 950 // FIFOs are flushed when this bit is changed. 951 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) 952 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) 953 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) 954 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) 955 #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 956 // ----------------------------------------------------------------------------- 957 // Field : PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH 958 // Description : Number of bits shifted out of TXSR before autopull or 959 // conditional pull. 960 // Write 0 for value of 32. 961 #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) 962 #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) 963 #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) 964 #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) 965 #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 966 // ----------------------------------------------------------------------------- 967 // Field : PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH 968 // Description : Number of bits shifted into RXSR before autopush or conditional 969 // push. 970 // Write 0 for value of 32. 971 #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) 972 #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) 973 #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) 974 #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) 975 #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 976 // ----------------------------------------------------------------------------- 977 // Field : PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR 978 // Description : 1 = shift out of output shift register to right. 0 = to left. 979 #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) 980 #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) 981 #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) 982 #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) 983 #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 984 // ----------------------------------------------------------------------------- 985 // Field : PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR 986 // Description : 1 = shift input shift register to right (data enters from 987 // left). 0 = to left. 988 #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) 989 #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) 990 #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) 991 #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) 992 #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 993 // ----------------------------------------------------------------------------- 994 // Field : PROC_PIO_SM0_SHIFTCTRL_AUTOPULL 995 // Description : Pull automatically when the output shift register is emptied 996 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) 997 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) 998 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) 999 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) 1000 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1001 // ----------------------------------------------------------------------------- 1002 // Field : PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH 1003 // Description : Push automatically when the input shift register is filled 1004 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) 1005 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) 1006 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) 1007 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) 1008 #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1009 // ============================================================================= 1010 // Register : PROC_PIO_SM0_ADDR 1011 // Description : Current instruction address of state machine 0 1012 #define PROC_PIO_SM0_ADDR_OFFSET _u(0x000000d8) 1013 #define PROC_PIO_SM0_ADDR_BITS _u(0x0000001f) 1014 #define PROC_PIO_SM0_ADDR_RESET _u(0x00000000) 1015 #define PROC_PIO_SM0_ADDR_WIDTH _u(32) 1016 #define PROC_PIO_SM0_ADDR_MSB _u(4) 1017 #define PROC_PIO_SM0_ADDR_LSB _u(0) 1018 #define PROC_PIO_SM0_ADDR_ACCESS "RO" 1019 // ============================================================================= 1020 // Register : PROC_PIO_SM0_INSTR 1021 // Description : Instruction currently being executed by state machine 0 1022 // Write to execute an instruction immediately (including jumps) 1023 // and then resume execution. 1024 #define PROC_PIO_SM0_INSTR_OFFSET _u(0x000000dc) 1025 #define PROC_PIO_SM0_INSTR_BITS _u(0x0000ffff) 1026 #define PROC_PIO_SM0_INSTR_RESET "-" 1027 #define PROC_PIO_SM0_INSTR_WIDTH _u(32) 1028 #define PROC_PIO_SM0_INSTR_MSB _u(15) 1029 #define PROC_PIO_SM0_INSTR_LSB _u(0) 1030 #define PROC_PIO_SM0_INSTR_ACCESS "RW" 1031 // ============================================================================= 1032 // Register : PROC_PIO_SM0_PINCTRL 1033 // Description : State machine pin control 1034 #define PROC_PIO_SM0_PINCTRL_OFFSET _u(0x000000e0) 1035 #define PROC_PIO_SM0_PINCTRL_BITS _u(0xffffffff) 1036 #define PROC_PIO_SM0_PINCTRL_RESET _u(0x14000000) 1037 #define PROC_PIO_SM0_PINCTRL_WIDTH _u(32) 1038 // ----------------------------------------------------------------------------- 1039 // Field : PROC_PIO_SM0_PINCTRL_SIDESET_COUNT 1040 // Description : The number of delay bits co-opted for side-set. Inclusive of 1041 // the enable bit, if present. 1042 #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) 1043 #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) 1044 #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) 1045 #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) 1046 #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1047 // ----------------------------------------------------------------------------- 1048 // Field : PROC_PIO_SM0_PINCTRL_SET_COUNT 1049 // Description : The number of pins asserted by a SET. Max of 5 1050 #define PROC_PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) 1051 #define PROC_PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) 1052 #define PROC_PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) 1053 #define PROC_PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) 1054 #define PROC_PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" 1055 // ----------------------------------------------------------------------------- 1056 // Field : PROC_PIO_SM0_PINCTRL_OUT_COUNT 1057 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1058 #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) 1059 #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) 1060 #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) 1061 #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) 1062 #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" 1063 // ----------------------------------------------------------------------------- 1064 // Field : PROC_PIO_SM0_PINCTRL_IN_BASE 1065 // Description : The virtual pin corresponding to IN bit 0 1066 #define PROC_PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) 1067 #define PROC_PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) 1068 #define PROC_PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) 1069 #define PROC_PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) 1070 #define PROC_PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" 1071 // ----------------------------------------------------------------------------- 1072 // Field : PROC_PIO_SM0_PINCTRL_SIDESET_BASE 1073 // Description : The virtual pin corresponding to delay field bit 0 1074 #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) 1075 #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) 1076 #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) 1077 #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) 1078 #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" 1079 // ----------------------------------------------------------------------------- 1080 // Field : PROC_PIO_SM0_PINCTRL_SET_BASE 1081 // Description : The virtual pin corresponding to SET bit 0 1082 #define PROC_PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) 1083 #define PROC_PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) 1084 #define PROC_PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) 1085 #define PROC_PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) 1086 #define PROC_PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" 1087 // ----------------------------------------------------------------------------- 1088 // Field : PROC_PIO_SM0_PINCTRL_OUT_BASE 1089 // Description : The virtual pin corresponding to OUT bit 0 1090 #define PROC_PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) 1091 #define PROC_PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) 1092 #define PROC_PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) 1093 #define PROC_PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) 1094 #define PROC_PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" 1095 // ============================================================================= 1096 // Register : PROC_PIO_SM0_DMACTRL_TX 1097 // Description : State machine DMA control 1098 #define PROC_PIO_SM0_DMACTRL_TX_OFFSET _u(0x000000e4) 1099 #define PROC_PIO_SM0_DMACTRL_TX_BITS _u(0xc0000f9f) 1100 #define PROC_PIO_SM0_DMACTRL_TX_RESET _u(0x00000104) 1101 #define PROC_PIO_SM0_DMACTRL_TX_WIDTH _u(32) 1102 // ----------------------------------------------------------------------------- 1103 // Field : PROC_PIO_SM0_DMACTRL_TX_DREQ_EN 1104 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1105 // are available 1106 // 0 - Don't assert DREQ 1107 #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_RESET _u(0x0) 1108 #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) 1109 #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_MSB _u(31) 1110 #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_LSB _u(31) 1111 #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_ACCESS "RW" 1112 // ----------------------------------------------------------------------------- 1113 // Field : PROC_PIO_SM0_DMACTRL_TX_ACTIVE 1114 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1115 // are available 1116 // 0 - Don't assert DREQ 1117 #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_RESET "-" 1118 #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) 1119 #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_MSB _u(30) 1120 #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_LSB _u(30) 1121 #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_ACCESS "RO" 1122 // ----------------------------------------------------------------------------- 1123 // Field : PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME 1124 // Description : Delay in number of bus cycles before successive DREQs are 1125 // generated. 1126 // Used to account for system bus latency in write data arriving 1127 // at the FIFO. 1128 #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) 1129 #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) 1130 #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_MSB _u(11) 1131 #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_LSB _u(7) 1132 #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_ACCESS "RW" 1133 // ----------------------------------------------------------------------------- 1134 // Field : PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD 1135 // Description : Threshold control. If there are no more than THRESHOLD items in 1136 // the TX FIFO, DMA dreq and/or the interrupt line is asserted. 1137 #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) 1138 #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1139 #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) 1140 #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) 1141 #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" 1142 // ============================================================================= 1143 // Register : PROC_PIO_SM0_DMACTRL_RX 1144 // Description : State machine DMA control 1145 #define PROC_PIO_SM0_DMACTRL_RX_OFFSET _u(0x000000e8) 1146 #define PROC_PIO_SM0_DMACTRL_RX_BITS _u(0xc0000f9f) 1147 #define PROC_PIO_SM0_DMACTRL_RX_RESET _u(0x00000104) 1148 #define PROC_PIO_SM0_DMACTRL_RX_WIDTH _u(32) 1149 // ----------------------------------------------------------------------------- 1150 // Field : PROC_PIO_SM0_DMACTRL_RX_DREQ_EN 1151 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1152 // are available 1153 // 0 - Don't assert DREQ 1154 #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_RESET _u(0x0) 1155 #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) 1156 #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_MSB _u(31) 1157 #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_LSB _u(31) 1158 #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_ACCESS "RW" 1159 // ----------------------------------------------------------------------------- 1160 // Field : PROC_PIO_SM0_DMACTRL_RX_ACTIVE 1161 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1162 // are available 1163 // 0 - Don't assert DREQ 1164 #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_RESET "-" 1165 #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) 1166 #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_MSB _u(30) 1167 #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_LSB _u(30) 1168 #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_ACCESS "RO" 1169 // ----------------------------------------------------------------------------- 1170 // Field : PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME 1171 // Description : Delay in number of bus cycles before successive DREQs are 1172 // generated. 1173 // Used to account for system bus latency in write data arriving 1174 // at the FIFO. 1175 #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) 1176 #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) 1177 #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_MSB _u(11) 1178 #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_LSB _u(7) 1179 #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_ACCESS "RW" 1180 // ----------------------------------------------------------------------------- 1181 // Field : PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD 1182 // Description : Threshold control. If there are at least THRESHOLD items in the 1183 // RX FIFO, DMA dreq and/or the interrupt line is asserted. 1184 #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) 1185 #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1186 #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) 1187 #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) 1188 #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" 1189 // ============================================================================= 1190 // Register : PROC_PIO_SM1_CLKDIV 1191 // Description : Clock divider register for state machine 1 1192 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 1193 #define PROC_PIO_SM1_CLKDIV_OFFSET _u(0x000000ec) 1194 #define PROC_PIO_SM1_CLKDIV_BITS _u(0xffffff00) 1195 #define PROC_PIO_SM1_CLKDIV_RESET _u(0x00010000) 1196 #define PROC_PIO_SM1_CLKDIV_WIDTH _u(32) 1197 // ----------------------------------------------------------------------------- 1198 // Field : PROC_PIO_SM1_CLKDIV_INT 1199 // Description : Effective frequency is sysclk/int. 1200 // Value of 0 is interpreted as max possible value 1201 #define PROC_PIO_SM1_CLKDIV_INT_RESET _u(0x0001) 1202 #define PROC_PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) 1203 #define PROC_PIO_SM1_CLKDIV_INT_MSB _u(31) 1204 #define PROC_PIO_SM1_CLKDIV_INT_LSB _u(16) 1205 #define PROC_PIO_SM1_CLKDIV_INT_ACCESS "RW" 1206 // ----------------------------------------------------------------------------- 1207 // Field : PROC_PIO_SM1_CLKDIV_FRAC 1208 // Description : Fractional part of clock divider 1209 #define PROC_PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) 1210 #define PROC_PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) 1211 #define PROC_PIO_SM1_CLKDIV_FRAC_MSB _u(15) 1212 #define PROC_PIO_SM1_CLKDIV_FRAC_LSB _u(8) 1213 #define PROC_PIO_SM1_CLKDIV_FRAC_ACCESS "RW" 1214 // ============================================================================= 1215 // Register : PROC_PIO_SM1_EXECCTRL 1216 // Description : Execution/behavioural settings for state machine 1 1217 #define PROC_PIO_SM1_EXECCTRL_OFFSET _u(0x000000f0) 1218 #define PROC_PIO_SM1_EXECCTRL_BITS _u(0xffffffbf) 1219 #define PROC_PIO_SM1_EXECCTRL_RESET _u(0x0001f000) 1220 #define PROC_PIO_SM1_EXECCTRL_WIDTH _u(32) 1221 // ----------------------------------------------------------------------------- 1222 // Field : PROC_PIO_SM1_EXECCTRL_EXEC_STALLED 1223 // Description : An instruction written to SMx_INSTR is stalled, and latched by 1224 // the 1225 // state machine. Will clear once the instruction completes. 1226 #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) 1227 #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) 1228 #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) 1229 #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) 1230 #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" 1231 // ----------------------------------------------------------------------------- 1232 // Field : PROC_PIO_SM1_EXECCTRL_SIDE_EN 1233 // Description : If 1, the delay MSB is used as side-set enable, rather than a 1234 // side-set data bit. This allows instructions to perform side-set 1235 // optionally, 1236 // rather than on every instruction. 1237 #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) 1238 #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) 1239 #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) 1240 #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) 1241 #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" 1242 // ----------------------------------------------------------------------------- 1243 // Field : PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR 1244 // Description : Side-set data is asserted to pin OEs instead of pin values 1245 #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) 1246 #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) 1247 #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) 1248 #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) 1249 #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 1250 // ----------------------------------------------------------------------------- 1251 // Field : PROC_PIO_SM1_EXECCTRL_JMP_PIN 1252 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 1253 // input mapping. 1254 #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) 1255 #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) 1256 #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) 1257 #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) 1258 #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" 1259 // ----------------------------------------------------------------------------- 1260 // Field : PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL 1261 // Description : Which data bit to use for inline OUT enable 1262 #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) 1263 #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) 1264 #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) 1265 #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) 1266 #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 1267 // ----------------------------------------------------------------------------- 1268 // Field : PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN 1269 // Description : If 1, use a bit of OUT data as an auxiliary write enable 1270 // When used in conjunction with OUT_STICKY, writes with an enable 1271 // of 0 will 1272 // deassert the latest pin write. This can create useful 1273 // masking/override behaviour 1274 // due to the priority ordering of state machine pin writes (SM0 < 1275 // SM1 < ...) 1276 #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) 1277 #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) 1278 #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) 1279 #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) 1280 #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 1281 // ----------------------------------------------------------------------------- 1282 // Field : PROC_PIO_SM1_EXECCTRL_OUT_STICKY 1283 // Description : Continuously assert the most recent OUT/SET to the pins 1284 #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) 1285 #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) 1286 #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) 1287 #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) 1288 #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" 1289 // ----------------------------------------------------------------------------- 1290 // Field : PROC_PIO_SM1_EXECCTRL_WRAP_TOP 1291 // Description : After reaching this address, execution is wrapped to 1292 // wrap_bottom. 1293 // If the instruction is a jump, and the jump condition is true, 1294 // the jump takes priority. 1295 #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) 1296 #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) 1297 #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) 1298 #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) 1299 #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" 1300 // ----------------------------------------------------------------------------- 1301 // Field : PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM 1302 // Description : After reaching wrap_top, execution is wrapped to this address. 1303 #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) 1304 #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) 1305 #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) 1306 #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) 1307 #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 1308 // ----------------------------------------------------------------------------- 1309 // Field : PROC_PIO_SM1_EXECCTRL_STATUS_SEL 1310 // Description : Comparison used for the MOV x, STATUS instruction. 1311 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 1312 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 1313 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) 1314 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) 1315 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(5) 1316 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) 1317 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" 1318 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) 1319 #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) 1320 // ----------------------------------------------------------------------------- 1321 // Field : PROC_PIO_SM1_EXECCTRL_STATUS_N 1322 // Description : Comparison level for the MOV x, STATUS instruction 1323 #define PROC_PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) 1324 #define PROC_PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) 1325 #define PROC_PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) 1326 #define PROC_PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) 1327 #define PROC_PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" 1328 // ============================================================================= 1329 // Register : PROC_PIO_SM1_SHIFTCTRL 1330 // Description : Control behaviour of the input/output shift registers for state 1331 // machine 1 1332 #define PROC_PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000f4) 1333 #define PROC_PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) 1334 #define PROC_PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) 1335 #define PROC_PIO_SM1_SHIFTCTRL_WIDTH _u(32) 1336 // ----------------------------------------------------------------------------- 1337 // Field : PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX 1338 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 1339 // as deep. 1340 // TX FIFO is disabled as a result (always reads as both full and 1341 // empty). 1342 // FIFOs are flushed when this bit is changed. 1343 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) 1344 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) 1345 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) 1346 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) 1347 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 1348 // ----------------------------------------------------------------------------- 1349 // Field : PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX 1350 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 1351 // as deep. 1352 // RX FIFO is disabled as a result (always reads as both full and 1353 // empty). 1354 // FIFOs are flushed when this bit is changed. 1355 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) 1356 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) 1357 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) 1358 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) 1359 #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 1360 // ----------------------------------------------------------------------------- 1361 // Field : PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH 1362 // Description : Number of bits shifted out of TXSR before autopull or 1363 // conditional pull. 1364 // Write 0 for value of 32. 1365 #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) 1366 #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) 1367 #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) 1368 #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) 1369 #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 1370 // ----------------------------------------------------------------------------- 1371 // Field : PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH 1372 // Description : Number of bits shifted into RXSR before autopush or conditional 1373 // push. 1374 // Write 0 for value of 32. 1375 #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) 1376 #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) 1377 #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) 1378 #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) 1379 #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 1380 // ----------------------------------------------------------------------------- 1381 // Field : PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR 1382 // Description : 1 = shift out of output shift register to right. 0 = to left. 1383 #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) 1384 #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) 1385 #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) 1386 #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) 1387 #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 1388 // ----------------------------------------------------------------------------- 1389 // Field : PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR 1390 // Description : 1 = shift input shift register to right (data enters from 1391 // left). 0 = to left. 1392 #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) 1393 #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) 1394 #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) 1395 #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) 1396 #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 1397 // ----------------------------------------------------------------------------- 1398 // Field : PROC_PIO_SM1_SHIFTCTRL_AUTOPULL 1399 // Description : Pull automatically when the output shift register is emptied 1400 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) 1401 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) 1402 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) 1403 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) 1404 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1405 // ----------------------------------------------------------------------------- 1406 // Field : PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH 1407 // Description : Push automatically when the input shift register is filled 1408 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) 1409 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) 1410 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) 1411 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) 1412 #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1413 // ============================================================================= 1414 // Register : PROC_PIO_SM1_ADDR 1415 // Description : Current instruction address of state machine 1 1416 #define PROC_PIO_SM1_ADDR_OFFSET _u(0x000000f8) 1417 #define PROC_PIO_SM1_ADDR_BITS _u(0x0000001f) 1418 #define PROC_PIO_SM1_ADDR_RESET _u(0x00000000) 1419 #define PROC_PIO_SM1_ADDR_WIDTH _u(32) 1420 #define PROC_PIO_SM1_ADDR_MSB _u(4) 1421 #define PROC_PIO_SM1_ADDR_LSB _u(0) 1422 #define PROC_PIO_SM1_ADDR_ACCESS "RO" 1423 // ============================================================================= 1424 // Register : PROC_PIO_SM1_INSTR 1425 // Description : Instruction currently being executed by state machine 1 1426 // Write to execute an instruction immediately (including jumps) 1427 // and then resume execution. 1428 #define PROC_PIO_SM1_INSTR_OFFSET _u(0x000000fc) 1429 #define PROC_PIO_SM1_INSTR_BITS _u(0x0000ffff) 1430 #define PROC_PIO_SM1_INSTR_RESET "-" 1431 #define PROC_PIO_SM1_INSTR_WIDTH _u(32) 1432 #define PROC_PIO_SM1_INSTR_MSB _u(15) 1433 #define PROC_PIO_SM1_INSTR_LSB _u(0) 1434 #define PROC_PIO_SM1_INSTR_ACCESS "RW" 1435 // ============================================================================= 1436 // Register : PROC_PIO_SM1_PINCTRL 1437 // Description : State machine pin control 1438 #define PROC_PIO_SM1_PINCTRL_OFFSET _u(0x00000100) 1439 #define PROC_PIO_SM1_PINCTRL_BITS _u(0xffffffff) 1440 #define PROC_PIO_SM1_PINCTRL_RESET _u(0x14000000) 1441 #define PROC_PIO_SM1_PINCTRL_WIDTH _u(32) 1442 // ----------------------------------------------------------------------------- 1443 // Field : PROC_PIO_SM1_PINCTRL_SIDESET_COUNT 1444 // Description : The number of delay bits co-opted for side-set. Inclusive of 1445 // the enable bit, if present. 1446 #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) 1447 #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) 1448 #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) 1449 #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) 1450 #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1451 // ----------------------------------------------------------------------------- 1452 // Field : PROC_PIO_SM1_PINCTRL_SET_COUNT 1453 // Description : The number of pins asserted by a SET. Max of 5 1454 #define PROC_PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) 1455 #define PROC_PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) 1456 #define PROC_PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) 1457 #define PROC_PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) 1458 #define PROC_PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" 1459 // ----------------------------------------------------------------------------- 1460 // Field : PROC_PIO_SM1_PINCTRL_OUT_COUNT 1461 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1462 #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) 1463 #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) 1464 #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) 1465 #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) 1466 #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" 1467 // ----------------------------------------------------------------------------- 1468 // Field : PROC_PIO_SM1_PINCTRL_IN_BASE 1469 // Description : The virtual pin corresponding to IN bit 0 1470 #define PROC_PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) 1471 #define PROC_PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) 1472 #define PROC_PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) 1473 #define PROC_PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) 1474 #define PROC_PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" 1475 // ----------------------------------------------------------------------------- 1476 // Field : PROC_PIO_SM1_PINCTRL_SIDESET_BASE 1477 // Description : The virtual pin corresponding to delay field bit 0 1478 #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) 1479 #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) 1480 #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) 1481 #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) 1482 #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" 1483 // ----------------------------------------------------------------------------- 1484 // Field : PROC_PIO_SM1_PINCTRL_SET_BASE 1485 // Description : The virtual pin corresponding to SET bit 0 1486 #define PROC_PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) 1487 #define PROC_PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) 1488 #define PROC_PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) 1489 #define PROC_PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) 1490 #define PROC_PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" 1491 // ----------------------------------------------------------------------------- 1492 // Field : PROC_PIO_SM1_PINCTRL_OUT_BASE 1493 // Description : The virtual pin corresponding to OUT bit 0 1494 #define PROC_PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) 1495 #define PROC_PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) 1496 #define PROC_PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) 1497 #define PROC_PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) 1498 #define PROC_PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" 1499 // ============================================================================= 1500 // Register : PROC_PIO_SM1_DMACTRL_TX 1501 // Description : State machine DMA control 1502 #define PROC_PIO_SM1_DMACTRL_TX_OFFSET _u(0x00000104) 1503 #define PROC_PIO_SM1_DMACTRL_TX_BITS _u(0xc0000f9f) 1504 #define PROC_PIO_SM1_DMACTRL_TX_RESET _u(0x00000104) 1505 #define PROC_PIO_SM1_DMACTRL_TX_WIDTH _u(32) 1506 // ----------------------------------------------------------------------------- 1507 // Field : PROC_PIO_SM1_DMACTRL_TX_DREQ_EN 1508 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1509 // are available 1510 // 0 - Don't assert DREQ 1511 #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_RESET _u(0x0) 1512 #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) 1513 #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_MSB _u(31) 1514 #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_LSB _u(31) 1515 #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_ACCESS "RW" 1516 // ----------------------------------------------------------------------------- 1517 // Field : PROC_PIO_SM1_DMACTRL_TX_ACTIVE 1518 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1519 // are available 1520 // 0 - Don't assert DREQ 1521 #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_RESET "-" 1522 #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) 1523 #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_MSB _u(30) 1524 #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_LSB _u(30) 1525 #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_ACCESS "RO" 1526 // ----------------------------------------------------------------------------- 1527 // Field : PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME 1528 // Description : Delay in number of bus cycles before successive DREQs are 1529 // generated. 1530 // Used to account for system bus latency in write data arriving 1531 // at the FIFO. 1532 #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) 1533 #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) 1534 #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_MSB _u(11) 1535 #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_LSB _u(7) 1536 #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_ACCESS "RW" 1537 // ----------------------------------------------------------------------------- 1538 // Field : PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD 1539 // Description : Threshold control. If there are no more than THRESHOLD items in 1540 // the TX FIFO, DMA dreq and/or the interrupt line is asserted. 1541 #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) 1542 #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1543 #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) 1544 #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) 1545 #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" 1546 // ============================================================================= 1547 // Register : PROC_PIO_SM1_DMACTRL_RX 1548 // Description : State machine DMA control 1549 #define PROC_PIO_SM1_DMACTRL_RX_OFFSET _u(0x00000108) 1550 #define PROC_PIO_SM1_DMACTRL_RX_BITS _u(0xc0000f9f) 1551 #define PROC_PIO_SM1_DMACTRL_RX_RESET _u(0x00000104) 1552 #define PROC_PIO_SM1_DMACTRL_RX_WIDTH _u(32) 1553 // ----------------------------------------------------------------------------- 1554 // Field : PROC_PIO_SM1_DMACTRL_RX_DREQ_EN 1555 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1556 // are available 1557 // 0 - Don't assert DREQ 1558 #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_RESET _u(0x0) 1559 #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) 1560 #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_MSB _u(31) 1561 #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_LSB _u(31) 1562 #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_ACCESS "RW" 1563 // ----------------------------------------------------------------------------- 1564 // Field : PROC_PIO_SM1_DMACTRL_RX_ACTIVE 1565 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1566 // are available 1567 // 0 - Don't assert DREQ 1568 #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_RESET "-" 1569 #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) 1570 #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_MSB _u(30) 1571 #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_LSB _u(30) 1572 #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_ACCESS "RO" 1573 // ----------------------------------------------------------------------------- 1574 // Field : PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME 1575 // Description : Delay in number of bus cycles before successive DREQs are 1576 // generated. 1577 // Used to account for system bus latency in write data arriving 1578 // at the FIFO. 1579 #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) 1580 #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) 1581 #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_MSB _u(11) 1582 #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_LSB _u(7) 1583 #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_ACCESS "RW" 1584 // ----------------------------------------------------------------------------- 1585 // Field : PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD 1586 // Description : Threshold control. If there are at least THRESHOLD items in the 1587 // RX FIFO, DMA dreq and/or the interrupt line is asserted. 1588 #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) 1589 #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1590 #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) 1591 #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) 1592 #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" 1593 // ============================================================================= 1594 // Register : PROC_PIO_SM2_CLKDIV 1595 // Description : Clock divider register for state machine 2 1596 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 1597 #define PROC_PIO_SM2_CLKDIV_OFFSET _u(0x0000010c) 1598 #define PROC_PIO_SM2_CLKDIV_BITS _u(0xffffff00) 1599 #define PROC_PIO_SM2_CLKDIV_RESET _u(0x00010000) 1600 #define PROC_PIO_SM2_CLKDIV_WIDTH _u(32) 1601 // ----------------------------------------------------------------------------- 1602 // Field : PROC_PIO_SM2_CLKDIV_INT 1603 // Description : Effective frequency is sysclk/int. 1604 // Value of 0 is interpreted as max possible value 1605 #define PROC_PIO_SM2_CLKDIV_INT_RESET _u(0x0001) 1606 #define PROC_PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) 1607 #define PROC_PIO_SM2_CLKDIV_INT_MSB _u(31) 1608 #define PROC_PIO_SM2_CLKDIV_INT_LSB _u(16) 1609 #define PROC_PIO_SM2_CLKDIV_INT_ACCESS "RW" 1610 // ----------------------------------------------------------------------------- 1611 // Field : PROC_PIO_SM2_CLKDIV_FRAC 1612 // Description : Fractional part of clock divider 1613 #define PROC_PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) 1614 #define PROC_PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) 1615 #define PROC_PIO_SM2_CLKDIV_FRAC_MSB _u(15) 1616 #define PROC_PIO_SM2_CLKDIV_FRAC_LSB _u(8) 1617 #define PROC_PIO_SM2_CLKDIV_FRAC_ACCESS "RW" 1618 // ============================================================================= 1619 // Register : PROC_PIO_SM2_EXECCTRL 1620 // Description : Execution/behavioural settings for state machine 2 1621 #define PROC_PIO_SM2_EXECCTRL_OFFSET _u(0x00000110) 1622 #define PROC_PIO_SM2_EXECCTRL_BITS _u(0xffffffbf) 1623 #define PROC_PIO_SM2_EXECCTRL_RESET _u(0x0001f000) 1624 #define PROC_PIO_SM2_EXECCTRL_WIDTH _u(32) 1625 // ----------------------------------------------------------------------------- 1626 // Field : PROC_PIO_SM2_EXECCTRL_EXEC_STALLED 1627 // Description : An instruction written to SMx_INSTR is stalled, and latched by 1628 // the 1629 // state machine. Will clear once the instruction completes. 1630 #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) 1631 #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) 1632 #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) 1633 #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) 1634 #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" 1635 // ----------------------------------------------------------------------------- 1636 // Field : PROC_PIO_SM2_EXECCTRL_SIDE_EN 1637 // Description : If 1, the delay MSB is used as side-set enable, rather than a 1638 // side-set data bit. This allows instructions to perform side-set 1639 // optionally, 1640 // rather than on every instruction. 1641 #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) 1642 #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) 1643 #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) 1644 #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) 1645 #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" 1646 // ----------------------------------------------------------------------------- 1647 // Field : PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR 1648 // Description : Side-set data is asserted to pin OEs instead of pin values 1649 #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) 1650 #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) 1651 #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) 1652 #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) 1653 #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 1654 // ----------------------------------------------------------------------------- 1655 // Field : PROC_PIO_SM2_EXECCTRL_JMP_PIN 1656 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 1657 // input mapping. 1658 #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) 1659 #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) 1660 #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) 1661 #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) 1662 #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" 1663 // ----------------------------------------------------------------------------- 1664 // Field : PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL 1665 // Description : Which data bit to use for inline OUT enable 1666 #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) 1667 #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) 1668 #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) 1669 #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) 1670 #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 1671 // ----------------------------------------------------------------------------- 1672 // Field : PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN 1673 // Description : If 1, use a bit of OUT data as an auxiliary write enable 1674 // When used in conjunction with OUT_STICKY, writes with an enable 1675 // of 0 will 1676 // deassert the latest pin write. This can create useful 1677 // masking/override behaviour 1678 // due to the priority ordering of state machine pin writes (SM0 < 1679 // SM1 < ...) 1680 #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) 1681 #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) 1682 #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) 1683 #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) 1684 #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 1685 // ----------------------------------------------------------------------------- 1686 // Field : PROC_PIO_SM2_EXECCTRL_OUT_STICKY 1687 // Description : Continuously assert the most recent OUT/SET to the pins 1688 #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) 1689 #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) 1690 #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) 1691 #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) 1692 #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" 1693 // ----------------------------------------------------------------------------- 1694 // Field : PROC_PIO_SM2_EXECCTRL_WRAP_TOP 1695 // Description : After reaching this address, execution is wrapped to 1696 // wrap_bottom. 1697 // If the instruction is a jump, and the jump condition is true, 1698 // the jump takes priority. 1699 #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) 1700 #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) 1701 #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) 1702 #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) 1703 #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" 1704 // ----------------------------------------------------------------------------- 1705 // Field : PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM 1706 // Description : After reaching wrap_top, execution is wrapped to this address. 1707 #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) 1708 #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) 1709 #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) 1710 #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) 1711 #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 1712 // ----------------------------------------------------------------------------- 1713 // Field : PROC_PIO_SM2_EXECCTRL_STATUS_SEL 1714 // Description : Comparison used for the MOV x, STATUS instruction. 1715 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 1716 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 1717 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) 1718 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) 1719 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(5) 1720 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) 1721 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" 1722 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) 1723 #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) 1724 // ----------------------------------------------------------------------------- 1725 // Field : PROC_PIO_SM2_EXECCTRL_STATUS_N 1726 // Description : Comparison level for the MOV x, STATUS instruction 1727 #define PROC_PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) 1728 #define PROC_PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) 1729 #define PROC_PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) 1730 #define PROC_PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) 1731 #define PROC_PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" 1732 // ============================================================================= 1733 // Register : PROC_PIO_SM2_SHIFTCTRL 1734 // Description : Control behaviour of the input/output shift registers for state 1735 // machine 2 1736 #define PROC_PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000114) 1737 #define PROC_PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) 1738 #define PROC_PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) 1739 #define PROC_PIO_SM2_SHIFTCTRL_WIDTH _u(32) 1740 // ----------------------------------------------------------------------------- 1741 // Field : PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX 1742 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 1743 // as deep. 1744 // TX FIFO is disabled as a result (always reads as both full and 1745 // empty). 1746 // FIFOs are flushed when this bit is changed. 1747 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) 1748 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) 1749 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) 1750 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) 1751 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 1752 // ----------------------------------------------------------------------------- 1753 // Field : PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX 1754 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 1755 // as deep. 1756 // RX FIFO is disabled as a result (always reads as both full and 1757 // empty). 1758 // FIFOs are flushed when this bit is changed. 1759 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) 1760 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) 1761 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) 1762 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) 1763 #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 1764 // ----------------------------------------------------------------------------- 1765 // Field : PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH 1766 // Description : Number of bits shifted out of TXSR before autopull or 1767 // conditional pull. 1768 // Write 0 for value of 32. 1769 #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) 1770 #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) 1771 #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) 1772 #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) 1773 #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 1774 // ----------------------------------------------------------------------------- 1775 // Field : PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH 1776 // Description : Number of bits shifted into RXSR before autopush or conditional 1777 // push. 1778 // Write 0 for value of 32. 1779 #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) 1780 #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) 1781 #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) 1782 #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) 1783 #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 1784 // ----------------------------------------------------------------------------- 1785 // Field : PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR 1786 // Description : 1 = shift out of output shift register to right. 0 = to left. 1787 #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) 1788 #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) 1789 #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) 1790 #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) 1791 #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 1792 // ----------------------------------------------------------------------------- 1793 // Field : PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR 1794 // Description : 1 = shift input shift register to right (data enters from 1795 // left). 0 = to left. 1796 #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) 1797 #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) 1798 #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) 1799 #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) 1800 #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 1801 // ----------------------------------------------------------------------------- 1802 // Field : PROC_PIO_SM2_SHIFTCTRL_AUTOPULL 1803 // Description : Pull automatically when the output shift register is emptied 1804 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) 1805 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) 1806 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) 1807 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) 1808 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1809 // ----------------------------------------------------------------------------- 1810 // Field : PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH 1811 // Description : Push automatically when the input shift register is filled 1812 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) 1813 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) 1814 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) 1815 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) 1816 #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1817 // ============================================================================= 1818 // Register : PROC_PIO_SM2_ADDR 1819 // Description : Current instruction address of state machine 2 1820 #define PROC_PIO_SM2_ADDR_OFFSET _u(0x00000118) 1821 #define PROC_PIO_SM2_ADDR_BITS _u(0x0000001f) 1822 #define PROC_PIO_SM2_ADDR_RESET _u(0x00000000) 1823 #define PROC_PIO_SM2_ADDR_WIDTH _u(32) 1824 #define PROC_PIO_SM2_ADDR_MSB _u(4) 1825 #define PROC_PIO_SM2_ADDR_LSB _u(0) 1826 #define PROC_PIO_SM2_ADDR_ACCESS "RO" 1827 // ============================================================================= 1828 // Register : PROC_PIO_SM2_INSTR 1829 // Description : Instruction currently being executed by state machine 2 1830 // Write to execute an instruction immediately (including jumps) 1831 // and then resume execution. 1832 #define PROC_PIO_SM2_INSTR_OFFSET _u(0x0000011c) 1833 #define PROC_PIO_SM2_INSTR_BITS _u(0x0000ffff) 1834 #define PROC_PIO_SM2_INSTR_RESET "-" 1835 #define PROC_PIO_SM2_INSTR_WIDTH _u(32) 1836 #define PROC_PIO_SM2_INSTR_MSB _u(15) 1837 #define PROC_PIO_SM2_INSTR_LSB _u(0) 1838 #define PROC_PIO_SM2_INSTR_ACCESS "RW" 1839 // ============================================================================= 1840 // Register : PROC_PIO_SM2_PINCTRL 1841 // Description : State machine pin control 1842 #define PROC_PIO_SM2_PINCTRL_OFFSET _u(0x00000120) 1843 #define PROC_PIO_SM2_PINCTRL_BITS _u(0xffffffff) 1844 #define PROC_PIO_SM2_PINCTRL_RESET _u(0x14000000) 1845 #define PROC_PIO_SM2_PINCTRL_WIDTH _u(32) 1846 // ----------------------------------------------------------------------------- 1847 // Field : PROC_PIO_SM2_PINCTRL_SIDESET_COUNT 1848 // Description : The number of delay bits co-opted for side-set. Inclusive of 1849 // the enable bit, if present. 1850 #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) 1851 #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) 1852 #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) 1853 #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) 1854 #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1855 // ----------------------------------------------------------------------------- 1856 // Field : PROC_PIO_SM2_PINCTRL_SET_COUNT 1857 // Description : The number of pins asserted by a SET. Max of 5 1858 #define PROC_PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) 1859 #define PROC_PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) 1860 #define PROC_PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) 1861 #define PROC_PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) 1862 #define PROC_PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" 1863 // ----------------------------------------------------------------------------- 1864 // Field : PROC_PIO_SM2_PINCTRL_OUT_COUNT 1865 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1866 #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) 1867 #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) 1868 #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) 1869 #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) 1870 #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" 1871 // ----------------------------------------------------------------------------- 1872 // Field : PROC_PIO_SM2_PINCTRL_IN_BASE 1873 // Description : The virtual pin corresponding to IN bit 0 1874 #define PROC_PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) 1875 #define PROC_PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) 1876 #define PROC_PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) 1877 #define PROC_PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) 1878 #define PROC_PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" 1879 // ----------------------------------------------------------------------------- 1880 // Field : PROC_PIO_SM2_PINCTRL_SIDESET_BASE 1881 // Description : The virtual pin corresponding to delay field bit 0 1882 #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) 1883 #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) 1884 #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) 1885 #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) 1886 #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" 1887 // ----------------------------------------------------------------------------- 1888 // Field : PROC_PIO_SM2_PINCTRL_SET_BASE 1889 // Description : The virtual pin corresponding to SET bit 0 1890 #define PROC_PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) 1891 #define PROC_PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) 1892 #define PROC_PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) 1893 #define PROC_PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) 1894 #define PROC_PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" 1895 // ----------------------------------------------------------------------------- 1896 // Field : PROC_PIO_SM2_PINCTRL_OUT_BASE 1897 // Description : The virtual pin corresponding to OUT bit 0 1898 #define PROC_PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) 1899 #define PROC_PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) 1900 #define PROC_PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) 1901 #define PROC_PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) 1902 #define PROC_PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" 1903 // ============================================================================= 1904 // Register : PROC_PIO_SM2_DMACTRL_TX 1905 // Description : State machine DMA control 1906 #define PROC_PIO_SM2_DMACTRL_TX_OFFSET _u(0x00000124) 1907 #define PROC_PIO_SM2_DMACTRL_TX_BITS _u(0xc0000f9f) 1908 #define PROC_PIO_SM2_DMACTRL_TX_RESET _u(0x00000104) 1909 #define PROC_PIO_SM2_DMACTRL_TX_WIDTH _u(32) 1910 // ----------------------------------------------------------------------------- 1911 // Field : PROC_PIO_SM2_DMACTRL_TX_DREQ_EN 1912 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1913 // are available 1914 // 0 - Don't assert DREQ 1915 #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_RESET _u(0x0) 1916 #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) 1917 #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_MSB _u(31) 1918 #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_LSB _u(31) 1919 #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_ACCESS "RW" 1920 // ----------------------------------------------------------------------------- 1921 // Field : PROC_PIO_SM2_DMACTRL_TX_ACTIVE 1922 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1923 // are available 1924 // 0 - Don't assert DREQ 1925 #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_RESET "-" 1926 #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) 1927 #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_MSB _u(30) 1928 #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_LSB _u(30) 1929 #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_ACCESS "RO" 1930 // ----------------------------------------------------------------------------- 1931 // Field : PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME 1932 // Description : Delay in number of bus cycles before successive DREQs are 1933 // generated. 1934 // Used to account for system bus latency in write data arriving 1935 // at the FIFO. 1936 #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) 1937 #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) 1938 #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_MSB _u(11) 1939 #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_LSB _u(7) 1940 #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_ACCESS "RW" 1941 // ----------------------------------------------------------------------------- 1942 // Field : PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD 1943 // Description : Threshold control. If there are no more than THRESHOLD items in 1944 // the TX FIFO, DMA dreq and/or the interrupt line is asserted. 1945 #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) 1946 #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1947 #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) 1948 #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) 1949 #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" 1950 // ============================================================================= 1951 // Register : PROC_PIO_SM2_DMACTRL_RX 1952 // Description : State machine DMA control 1953 #define PROC_PIO_SM2_DMACTRL_RX_OFFSET _u(0x00000128) 1954 #define PROC_PIO_SM2_DMACTRL_RX_BITS _u(0xc0000f9f) 1955 #define PROC_PIO_SM2_DMACTRL_RX_RESET _u(0x00000104) 1956 #define PROC_PIO_SM2_DMACTRL_RX_WIDTH _u(32) 1957 // ----------------------------------------------------------------------------- 1958 // Field : PROC_PIO_SM2_DMACTRL_RX_DREQ_EN 1959 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1960 // are available 1961 // 0 - Don't assert DREQ 1962 #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_RESET _u(0x0) 1963 #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) 1964 #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_MSB _u(31) 1965 #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_LSB _u(31) 1966 #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_ACCESS "RW" 1967 // ----------------------------------------------------------------------------- 1968 // Field : PROC_PIO_SM2_DMACTRL_RX_ACTIVE 1969 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 1970 // are available 1971 // 0 - Don't assert DREQ 1972 #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_RESET "-" 1973 #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) 1974 #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_MSB _u(30) 1975 #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_LSB _u(30) 1976 #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_ACCESS "RO" 1977 // ----------------------------------------------------------------------------- 1978 // Field : PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME 1979 // Description : Delay in number of bus cycles before successive DREQs are 1980 // generated. 1981 // Used to account for system bus latency in write data arriving 1982 // at the FIFO. 1983 #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) 1984 #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) 1985 #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_MSB _u(11) 1986 #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_LSB _u(7) 1987 #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_ACCESS "RW" 1988 // ----------------------------------------------------------------------------- 1989 // Field : PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD 1990 // Description : Threshold control. If there are at least THRESHOLD items in the 1991 // RX FIFO, DMA dreq and/or the interrupt line is asserted. 1992 #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) 1993 #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) 1994 #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) 1995 #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) 1996 #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" 1997 // ============================================================================= 1998 // Register : PROC_PIO_SM3_CLKDIV 1999 // Description : Clock divider register for state machine 3 2000 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 2001 #define PROC_PIO_SM3_CLKDIV_OFFSET _u(0x0000012c) 2002 #define PROC_PIO_SM3_CLKDIV_BITS _u(0xffffff00) 2003 #define PROC_PIO_SM3_CLKDIV_RESET _u(0x00010000) 2004 #define PROC_PIO_SM3_CLKDIV_WIDTH _u(32) 2005 // ----------------------------------------------------------------------------- 2006 // Field : PROC_PIO_SM3_CLKDIV_INT 2007 // Description : Effective frequency is sysclk/int. 2008 // Value of 0 is interpreted as max possible value 2009 #define PROC_PIO_SM3_CLKDIV_INT_RESET _u(0x0001) 2010 #define PROC_PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) 2011 #define PROC_PIO_SM3_CLKDIV_INT_MSB _u(31) 2012 #define PROC_PIO_SM3_CLKDIV_INT_LSB _u(16) 2013 #define PROC_PIO_SM3_CLKDIV_INT_ACCESS "RW" 2014 // ----------------------------------------------------------------------------- 2015 // Field : PROC_PIO_SM3_CLKDIV_FRAC 2016 // Description : Fractional part of clock divider 2017 #define PROC_PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) 2018 #define PROC_PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) 2019 #define PROC_PIO_SM3_CLKDIV_FRAC_MSB _u(15) 2020 #define PROC_PIO_SM3_CLKDIV_FRAC_LSB _u(8) 2021 #define PROC_PIO_SM3_CLKDIV_FRAC_ACCESS "RW" 2022 // ============================================================================= 2023 // Register : PROC_PIO_SM3_EXECCTRL 2024 // Description : Execution/behavioural settings for state machine 3 2025 #define PROC_PIO_SM3_EXECCTRL_OFFSET _u(0x00000130) 2026 #define PROC_PIO_SM3_EXECCTRL_BITS _u(0xffffffbf) 2027 #define PROC_PIO_SM3_EXECCTRL_RESET _u(0x0001f000) 2028 #define PROC_PIO_SM3_EXECCTRL_WIDTH _u(32) 2029 // ----------------------------------------------------------------------------- 2030 // Field : PROC_PIO_SM3_EXECCTRL_EXEC_STALLED 2031 // Description : An instruction written to SMx_INSTR is stalled, and latched by 2032 // the 2033 // state machine. Will clear once the instruction completes. 2034 #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) 2035 #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) 2036 #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) 2037 #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) 2038 #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" 2039 // ----------------------------------------------------------------------------- 2040 // Field : PROC_PIO_SM3_EXECCTRL_SIDE_EN 2041 // Description : If 1, the delay MSB is used as side-set enable, rather than a 2042 // side-set data bit. This allows instructions to perform side-set 2043 // optionally, 2044 // rather than on every instruction. 2045 #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) 2046 #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) 2047 #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) 2048 #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) 2049 #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" 2050 // ----------------------------------------------------------------------------- 2051 // Field : PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR 2052 // Description : Side-set data is asserted to pin OEs instead of pin values 2053 #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) 2054 #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) 2055 #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) 2056 #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) 2057 #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 2058 // ----------------------------------------------------------------------------- 2059 // Field : PROC_PIO_SM3_EXECCTRL_JMP_PIN 2060 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 2061 // input mapping. 2062 #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) 2063 #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) 2064 #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) 2065 #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) 2066 #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" 2067 // ----------------------------------------------------------------------------- 2068 // Field : PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL 2069 // Description : Which data bit to use for inline OUT enable 2070 #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) 2071 #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) 2072 #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) 2073 #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) 2074 #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 2075 // ----------------------------------------------------------------------------- 2076 // Field : PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN 2077 // Description : If 1, use a bit of OUT data as an auxiliary write enable 2078 // When used in conjunction with OUT_STICKY, writes with an enable 2079 // of 0 will 2080 // deassert the latest pin write. This can create useful 2081 // masking/override behaviour 2082 // due to the priority ordering of state machine pin writes (SM0 < 2083 // SM1 < ...) 2084 #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) 2085 #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) 2086 #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) 2087 #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) 2088 #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 2089 // ----------------------------------------------------------------------------- 2090 // Field : PROC_PIO_SM3_EXECCTRL_OUT_STICKY 2091 // Description : Continuously assert the most recent OUT/SET to the pins 2092 #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) 2093 #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) 2094 #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) 2095 #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) 2096 #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" 2097 // ----------------------------------------------------------------------------- 2098 // Field : PROC_PIO_SM3_EXECCTRL_WRAP_TOP 2099 // Description : After reaching this address, execution is wrapped to 2100 // wrap_bottom. 2101 // If the instruction is a jump, and the jump condition is true, 2102 // the jump takes priority. 2103 #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) 2104 #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) 2105 #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) 2106 #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) 2107 #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" 2108 // ----------------------------------------------------------------------------- 2109 // Field : PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM 2110 // Description : After reaching wrap_top, execution is wrapped to this address. 2111 #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) 2112 #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) 2113 #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) 2114 #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) 2115 #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 2116 // ----------------------------------------------------------------------------- 2117 // Field : PROC_PIO_SM3_EXECCTRL_STATUS_SEL 2118 // Description : Comparison used for the MOV x, STATUS instruction. 2119 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 2120 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 2121 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) 2122 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) 2123 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(5) 2124 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) 2125 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" 2126 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) 2127 #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) 2128 // ----------------------------------------------------------------------------- 2129 // Field : PROC_PIO_SM3_EXECCTRL_STATUS_N 2130 // Description : Comparison level for the MOV x, STATUS instruction 2131 #define PROC_PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) 2132 #define PROC_PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) 2133 #define PROC_PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) 2134 #define PROC_PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) 2135 #define PROC_PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" 2136 // ============================================================================= 2137 // Register : PROC_PIO_SM3_SHIFTCTRL 2138 // Description : Control behaviour of the input/output shift registers for state 2139 // machine 3 2140 #define PROC_PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000134) 2141 #define PROC_PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) 2142 #define PROC_PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) 2143 #define PROC_PIO_SM3_SHIFTCTRL_WIDTH _u(32) 2144 // ----------------------------------------------------------------------------- 2145 // Field : PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX 2146 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 2147 // as deep. 2148 // TX FIFO is disabled as a result (always reads as both full and 2149 // empty). 2150 // FIFOs are flushed when this bit is changed. 2151 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) 2152 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) 2153 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) 2154 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) 2155 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 2156 // ----------------------------------------------------------------------------- 2157 // Field : PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX 2158 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 2159 // as deep. 2160 // RX FIFO is disabled as a result (always reads as both full and 2161 // empty). 2162 // FIFOs are flushed when this bit is changed. 2163 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) 2164 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) 2165 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) 2166 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) 2167 #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 2168 // ----------------------------------------------------------------------------- 2169 // Field : PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH 2170 // Description : Number of bits shifted out of TXSR before autopull or 2171 // conditional pull. 2172 // Write 0 for value of 32. 2173 #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) 2174 #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) 2175 #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) 2176 #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) 2177 #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 2178 // ----------------------------------------------------------------------------- 2179 // Field : PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH 2180 // Description : Number of bits shifted into RXSR before autopush or conditional 2181 // push. 2182 // Write 0 for value of 32. 2183 #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) 2184 #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) 2185 #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) 2186 #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) 2187 #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 2188 // ----------------------------------------------------------------------------- 2189 // Field : PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR 2190 // Description : 1 = shift out of output shift register to right. 0 = to left. 2191 #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) 2192 #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) 2193 #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) 2194 #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) 2195 #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 2196 // ----------------------------------------------------------------------------- 2197 // Field : PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR 2198 // Description : 1 = shift input shift register to right (data enters from 2199 // left). 0 = to left. 2200 #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) 2201 #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) 2202 #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) 2203 #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) 2204 #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 2205 // ----------------------------------------------------------------------------- 2206 // Field : PROC_PIO_SM3_SHIFTCTRL_AUTOPULL 2207 // Description : Pull automatically when the output shift register is emptied 2208 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) 2209 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) 2210 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) 2211 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) 2212 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" 2213 // ----------------------------------------------------------------------------- 2214 // Field : PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH 2215 // Description : Push automatically when the input shift register is filled 2216 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) 2217 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) 2218 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) 2219 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) 2220 #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 2221 // ============================================================================= 2222 // Register : PROC_PIO_SM3_ADDR 2223 // Description : Current instruction address of state machine 3 2224 #define PROC_PIO_SM3_ADDR_OFFSET _u(0x00000138) 2225 #define PROC_PIO_SM3_ADDR_BITS _u(0x0000001f) 2226 #define PROC_PIO_SM3_ADDR_RESET _u(0x00000000) 2227 #define PROC_PIO_SM3_ADDR_WIDTH _u(32) 2228 #define PROC_PIO_SM3_ADDR_MSB _u(4) 2229 #define PROC_PIO_SM3_ADDR_LSB _u(0) 2230 #define PROC_PIO_SM3_ADDR_ACCESS "RO" 2231 // ============================================================================= 2232 // Register : PROC_PIO_SM3_INSTR 2233 // Description : Instruction currently being executed by state machine 3 2234 // Write to execute an instruction immediately (including jumps) 2235 // and then resume execution. 2236 #define PROC_PIO_SM3_INSTR_OFFSET _u(0x0000013c) 2237 #define PROC_PIO_SM3_INSTR_BITS _u(0x0000ffff) 2238 #define PROC_PIO_SM3_INSTR_RESET "-" 2239 #define PROC_PIO_SM3_INSTR_WIDTH _u(32) 2240 #define PROC_PIO_SM3_INSTR_MSB _u(15) 2241 #define PROC_PIO_SM3_INSTR_LSB _u(0) 2242 #define PROC_PIO_SM3_INSTR_ACCESS "RW" 2243 // ============================================================================= 2244 // Register : PROC_PIO_SM3_PINCTRL 2245 // Description : State machine pin control 2246 #define PROC_PIO_SM3_PINCTRL_OFFSET _u(0x00000140) 2247 #define PROC_PIO_SM3_PINCTRL_BITS _u(0xffffffff) 2248 #define PROC_PIO_SM3_PINCTRL_RESET _u(0x14000000) 2249 #define PROC_PIO_SM3_PINCTRL_WIDTH _u(32) 2250 // ----------------------------------------------------------------------------- 2251 // Field : PROC_PIO_SM3_PINCTRL_SIDESET_COUNT 2252 // Description : The number of delay bits co-opted for side-set. Inclusive of 2253 // the enable bit, if present. 2254 #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) 2255 #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) 2256 #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) 2257 #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) 2258 #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" 2259 // ----------------------------------------------------------------------------- 2260 // Field : PROC_PIO_SM3_PINCTRL_SET_COUNT 2261 // Description : The number of pins asserted by a SET. Max of 5 2262 #define PROC_PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) 2263 #define PROC_PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) 2264 #define PROC_PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) 2265 #define PROC_PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) 2266 #define PROC_PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" 2267 // ----------------------------------------------------------------------------- 2268 // Field : PROC_PIO_SM3_PINCTRL_OUT_COUNT 2269 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 2270 #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) 2271 #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) 2272 #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) 2273 #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) 2274 #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" 2275 // ----------------------------------------------------------------------------- 2276 // Field : PROC_PIO_SM3_PINCTRL_IN_BASE 2277 // Description : The virtual pin corresponding to IN bit 0 2278 #define PROC_PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) 2279 #define PROC_PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) 2280 #define PROC_PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) 2281 #define PROC_PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) 2282 #define PROC_PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" 2283 // ----------------------------------------------------------------------------- 2284 // Field : PROC_PIO_SM3_PINCTRL_SIDESET_BASE 2285 // Description : The virtual pin corresponding to delay field bit 0 2286 #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) 2287 #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) 2288 #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) 2289 #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) 2290 #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" 2291 // ----------------------------------------------------------------------------- 2292 // Field : PROC_PIO_SM3_PINCTRL_SET_BASE 2293 // Description : The virtual pin corresponding to SET bit 0 2294 #define PROC_PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) 2295 #define PROC_PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) 2296 #define PROC_PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) 2297 #define PROC_PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) 2298 #define PROC_PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" 2299 // ----------------------------------------------------------------------------- 2300 // Field : PROC_PIO_SM3_PINCTRL_OUT_BASE 2301 // Description : The virtual pin corresponding to OUT bit 0 2302 #define PROC_PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) 2303 #define PROC_PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) 2304 #define PROC_PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) 2305 #define PROC_PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) 2306 #define PROC_PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" 2307 // ============================================================================= 2308 // Register : PROC_PIO_SM3_DMACTRL_TX 2309 // Description : State machine DMA control 2310 #define PROC_PIO_SM3_DMACTRL_TX_OFFSET _u(0x00000144) 2311 #define PROC_PIO_SM3_DMACTRL_TX_BITS _u(0xc0000f9f) 2312 #define PROC_PIO_SM3_DMACTRL_TX_RESET _u(0x00000104) 2313 #define PROC_PIO_SM3_DMACTRL_TX_WIDTH _u(32) 2314 // ----------------------------------------------------------------------------- 2315 // Field : PROC_PIO_SM3_DMACTRL_TX_DREQ_EN 2316 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 2317 // are available 2318 // 0 - Don't assert DREQ 2319 #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_RESET _u(0x0) 2320 #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) 2321 #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_MSB _u(31) 2322 #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_LSB _u(31) 2323 #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_ACCESS "RW" 2324 // ----------------------------------------------------------------------------- 2325 // Field : PROC_PIO_SM3_DMACTRL_TX_ACTIVE 2326 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 2327 // are available 2328 // 0 - Don't assert DREQ 2329 #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_RESET "-" 2330 #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) 2331 #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_MSB _u(30) 2332 #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_LSB _u(30) 2333 #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_ACCESS "RO" 2334 // ----------------------------------------------------------------------------- 2335 // Field : PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME 2336 // Description : Delay in number of bus cycles before successive DREQs are 2337 // generated. 2338 // Used to account for system bus latency in write data arriving 2339 // at the FIFO. 2340 #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) 2341 #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) 2342 #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_MSB _u(11) 2343 #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_LSB _u(7) 2344 #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_ACCESS "RW" 2345 // ----------------------------------------------------------------------------- 2346 // Field : PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD 2347 // Description : Threshold control. If there are no more than THRESHOLD items in 2348 // the TX FIFO, DMA dreq and/or the interrupt line is asserted. 2349 #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) 2350 #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) 2351 #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) 2352 #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) 2353 #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" 2354 // ============================================================================= 2355 // Register : PROC_PIO_SM3_DMACTRL_RX 2356 // Description : State machine DMA control 2357 #define PROC_PIO_SM3_DMACTRL_RX_OFFSET _u(0x00000148) 2358 #define PROC_PIO_SM3_DMACTRL_RX_BITS _u(0xc0000f9f) 2359 #define PROC_PIO_SM3_DMACTRL_RX_RESET _u(0x00000104) 2360 #define PROC_PIO_SM3_DMACTRL_RX_WIDTH _u(32) 2361 // ----------------------------------------------------------------------------- 2362 // Field : PROC_PIO_SM3_DMACTRL_RX_DREQ_EN 2363 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 2364 // are available 2365 // 0 - Don't assert DREQ 2366 #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_RESET _u(0x0) 2367 #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) 2368 #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_MSB _u(31) 2369 #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_LSB _u(31) 2370 #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_ACCESS "RW" 2371 // ----------------------------------------------------------------------------- 2372 // Field : PROC_PIO_SM3_DMACTRL_RX_ACTIVE 2373 // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces 2374 // are available 2375 // 0 - Don't assert DREQ 2376 #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_RESET "-" 2377 #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) 2378 #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_MSB _u(30) 2379 #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_LSB _u(30) 2380 #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_ACCESS "RO" 2381 // ----------------------------------------------------------------------------- 2382 // Field : PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME 2383 // Description : Delay in number of bus cycles before successive DREQs are 2384 // generated. 2385 // Used to account for system bus latency in write data arriving 2386 // at the FIFO. 2387 #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) 2388 #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) 2389 #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_MSB _u(11) 2390 #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_LSB _u(7) 2391 #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_ACCESS "RW" 2392 // ----------------------------------------------------------------------------- 2393 // Field : PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD 2394 // Description : Threshold control. If there are at least THRESHOLD items in the 2395 // RX FIFO, DMA dreq and/or the interrupt line is asserted. 2396 #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) 2397 #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) 2398 #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) 2399 #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) 2400 #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" 2401 // ============================================================================= 2402 // Register : PROC_PIO_INTR 2403 // Description : Raw Interrupts 2404 #define PROC_PIO_INTR_OFFSET _u(0x0000014c) 2405 #define PROC_PIO_INTR_BITS _u(0x00000fff) 2406 #define PROC_PIO_INTR_RESET _u(0x00000000) 2407 #define PROC_PIO_INTR_WIDTH _u(32) 2408 // ----------------------------------------------------------------------------- 2409 // Field : PROC_PIO_INTR_SM3 2410 // Description : None 2411 #define PROC_PIO_INTR_SM3_RESET _u(0x0) 2412 #define PROC_PIO_INTR_SM3_BITS _u(0x00000800) 2413 #define PROC_PIO_INTR_SM3_MSB _u(11) 2414 #define PROC_PIO_INTR_SM3_LSB _u(11) 2415 #define PROC_PIO_INTR_SM3_ACCESS "RO" 2416 // ----------------------------------------------------------------------------- 2417 // Field : PROC_PIO_INTR_SM2 2418 // Description : None 2419 #define PROC_PIO_INTR_SM2_RESET _u(0x0) 2420 #define PROC_PIO_INTR_SM2_BITS _u(0x00000400) 2421 #define PROC_PIO_INTR_SM2_MSB _u(10) 2422 #define PROC_PIO_INTR_SM2_LSB _u(10) 2423 #define PROC_PIO_INTR_SM2_ACCESS "RO" 2424 // ----------------------------------------------------------------------------- 2425 // Field : PROC_PIO_INTR_SM1 2426 // Description : None 2427 #define PROC_PIO_INTR_SM1_RESET _u(0x0) 2428 #define PROC_PIO_INTR_SM1_BITS _u(0x00000200) 2429 #define PROC_PIO_INTR_SM1_MSB _u(9) 2430 #define PROC_PIO_INTR_SM1_LSB _u(9) 2431 #define PROC_PIO_INTR_SM1_ACCESS "RO" 2432 // ----------------------------------------------------------------------------- 2433 // Field : PROC_PIO_INTR_SM0 2434 // Description : None 2435 #define PROC_PIO_INTR_SM0_RESET _u(0x0) 2436 #define PROC_PIO_INTR_SM0_BITS _u(0x00000100) 2437 #define PROC_PIO_INTR_SM0_MSB _u(8) 2438 #define PROC_PIO_INTR_SM0_LSB _u(8) 2439 #define PROC_PIO_INTR_SM0_ACCESS "RO" 2440 // ----------------------------------------------------------------------------- 2441 // Field : PROC_PIO_INTR_SM3_TXNFULL 2442 // Description : None 2443 #define PROC_PIO_INTR_SM3_TXNFULL_RESET _u(0x0) 2444 #define PROC_PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) 2445 #define PROC_PIO_INTR_SM3_TXNFULL_MSB _u(7) 2446 #define PROC_PIO_INTR_SM3_TXNFULL_LSB _u(7) 2447 #define PROC_PIO_INTR_SM3_TXNFULL_ACCESS "RO" 2448 // ----------------------------------------------------------------------------- 2449 // Field : PROC_PIO_INTR_SM2_TXNFULL 2450 // Description : None 2451 #define PROC_PIO_INTR_SM2_TXNFULL_RESET _u(0x0) 2452 #define PROC_PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) 2453 #define PROC_PIO_INTR_SM2_TXNFULL_MSB _u(6) 2454 #define PROC_PIO_INTR_SM2_TXNFULL_LSB _u(6) 2455 #define PROC_PIO_INTR_SM2_TXNFULL_ACCESS "RO" 2456 // ----------------------------------------------------------------------------- 2457 // Field : PROC_PIO_INTR_SM1_TXNFULL 2458 // Description : None 2459 #define PROC_PIO_INTR_SM1_TXNFULL_RESET _u(0x0) 2460 #define PROC_PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) 2461 #define PROC_PIO_INTR_SM1_TXNFULL_MSB _u(5) 2462 #define PROC_PIO_INTR_SM1_TXNFULL_LSB _u(5) 2463 #define PROC_PIO_INTR_SM1_TXNFULL_ACCESS "RO" 2464 // ----------------------------------------------------------------------------- 2465 // Field : PROC_PIO_INTR_SM0_TXNFULL 2466 // Description : None 2467 #define PROC_PIO_INTR_SM0_TXNFULL_RESET _u(0x0) 2468 #define PROC_PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) 2469 #define PROC_PIO_INTR_SM0_TXNFULL_MSB _u(4) 2470 #define PROC_PIO_INTR_SM0_TXNFULL_LSB _u(4) 2471 #define PROC_PIO_INTR_SM0_TXNFULL_ACCESS "RO" 2472 // ----------------------------------------------------------------------------- 2473 // Field : PROC_PIO_INTR_SM3_RXNEMPTY 2474 // Description : None 2475 #define PROC_PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) 2476 #define PROC_PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) 2477 #define PROC_PIO_INTR_SM3_RXNEMPTY_MSB _u(3) 2478 #define PROC_PIO_INTR_SM3_RXNEMPTY_LSB _u(3) 2479 #define PROC_PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" 2480 // ----------------------------------------------------------------------------- 2481 // Field : PROC_PIO_INTR_SM2_RXNEMPTY 2482 // Description : None 2483 #define PROC_PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) 2484 #define PROC_PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) 2485 #define PROC_PIO_INTR_SM2_RXNEMPTY_MSB _u(2) 2486 #define PROC_PIO_INTR_SM2_RXNEMPTY_LSB _u(2) 2487 #define PROC_PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" 2488 // ----------------------------------------------------------------------------- 2489 // Field : PROC_PIO_INTR_SM1_RXNEMPTY 2490 // Description : None 2491 #define PROC_PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) 2492 #define PROC_PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) 2493 #define PROC_PIO_INTR_SM1_RXNEMPTY_MSB _u(1) 2494 #define PROC_PIO_INTR_SM1_RXNEMPTY_LSB _u(1) 2495 #define PROC_PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" 2496 // ----------------------------------------------------------------------------- 2497 // Field : PROC_PIO_INTR_SM0_RXNEMPTY 2498 // Description : None 2499 #define PROC_PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) 2500 #define PROC_PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) 2501 #define PROC_PIO_INTR_SM0_RXNEMPTY_MSB _u(0) 2502 #define PROC_PIO_INTR_SM0_RXNEMPTY_LSB _u(0) 2503 #define PROC_PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" 2504 // ============================================================================= 2505 // Register : PROC_PIO_IRQ0_INTE 2506 // Description : Interrupt Enable for irq0 2507 #define PROC_PIO_IRQ0_INTE_OFFSET _u(0x00000150) 2508 #define PROC_PIO_IRQ0_INTE_BITS _u(0x00000fff) 2509 #define PROC_PIO_IRQ0_INTE_RESET _u(0x00000000) 2510 #define PROC_PIO_IRQ0_INTE_WIDTH _u(32) 2511 // ----------------------------------------------------------------------------- 2512 // Field : PROC_PIO_IRQ0_INTE_SM3 2513 // Description : None 2514 #define PROC_PIO_IRQ0_INTE_SM3_RESET _u(0x0) 2515 #define PROC_PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) 2516 #define PROC_PIO_IRQ0_INTE_SM3_MSB _u(11) 2517 #define PROC_PIO_IRQ0_INTE_SM3_LSB _u(11) 2518 #define PROC_PIO_IRQ0_INTE_SM3_ACCESS "RW" 2519 // ----------------------------------------------------------------------------- 2520 // Field : PROC_PIO_IRQ0_INTE_SM2 2521 // Description : None 2522 #define PROC_PIO_IRQ0_INTE_SM2_RESET _u(0x0) 2523 #define PROC_PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) 2524 #define PROC_PIO_IRQ0_INTE_SM2_MSB _u(10) 2525 #define PROC_PIO_IRQ0_INTE_SM2_LSB _u(10) 2526 #define PROC_PIO_IRQ0_INTE_SM2_ACCESS "RW" 2527 // ----------------------------------------------------------------------------- 2528 // Field : PROC_PIO_IRQ0_INTE_SM1 2529 // Description : None 2530 #define PROC_PIO_IRQ0_INTE_SM1_RESET _u(0x0) 2531 #define PROC_PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) 2532 #define PROC_PIO_IRQ0_INTE_SM1_MSB _u(9) 2533 #define PROC_PIO_IRQ0_INTE_SM1_LSB _u(9) 2534 #define PROC_PIO_IRQ0_INTE_SM1_ACCESS "RW" 2535 // ----------------------------------------------------------------------------- 2536 // Field : PROC_PIO_IRQ0_INTE_SM0 2537 // Description : None 2538 #define PROC_PIO_IRQ0_INTE_SM0_RESET _u(0x0) 2539 #define PROC_PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) 2540 #define PROC_PIO_IRQ0_INTE_SM0_MSB _u(8) 2541 #define PROC_PIO_IRQ0_INTE_SM0_LSB _u(8) 2542 #define PROC_PIO_IRQ0_INTE_SM0_ACCESS "RW" 2543 // ----------------------------------------------------------------------------- 2544 // Field : PROC_PIO_IRQ0_INTE_SM3_TXNFULL 2545 // Description : None 2546 #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) 2547 #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) 2548 #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) 2549 #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) 2550 #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" 2551 // ----------------------------------------------------------------------------- 2552 // Field : PROC_PIO_IRQ0_INTE_SM2_TXNFULL 2553 // Description : None 2554 #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) 2555 #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) 2556 #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) 2557 #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) 2558 #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" 2559 // ----------------------------------------------------------------------------- 2560 // Field : PROC_PIO_IRQ0_INTE_SM1_TXNFULL 2561 // Description : None 2562 #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) 2563 #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) 2564 #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) 2565 #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) 2566 #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" 2567 // ----------------------------------------------------------------------------- 2568 // Field : PROC_PIO_IRQ0_INTE_SM0_TXNFULL 2569 // Description : None 2570 #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) 2571 #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) 2572 #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) 2573 #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) 2574 #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" 2575 // ----------------------------------------------------------------------------- 2576 // Field : PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY 2577 // Description : None 2578 #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) 2579 #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) 2580 #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) 2581 #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) 2582 #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" 2583 // ----------------------------------------------------------------------------- 2584 // Field : PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY 2585 // Description : None 2586 #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) 2587 #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) 2588 #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) 2589 #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) 2590 #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" 2591 // ----------------------------------------------------------------------------- 2592 // Field : PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY 2593 // Description : None 2594 #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) 2595 #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) 2596 #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) 2597 #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) 2598 #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" 2599 // ----------------------------------------------------------------------------- 2600 // Field : PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY 2601 // Description : None 2602 #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) 2603 #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) 2604 #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) 2605 #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) 2606 #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" 2607 // ============================================================================= 2608 // Register : PROC_PIO_IRQ0_INTF 2609 // Description : Interrupt Force for irq0 2610 #define PROC_PIO_IRQ0_INTF_OFFSET _u(0x00000154) 2611 #define PROC_PIO_IRQ0_INTF_BITS _u(0x00000fff) 2612 #define PROC_PIO_IRQ0_INTF_RESET _u(0x00000000) 2613 #define PROC_PIO_IRQ0_INTF_WIDTH _u(32) 2614 // ----------------------------------------------------------------------------- 2615 // Field : PROC_PIO_IRQ0_INTF_SM3 2616 // Description : None 2617 #define PROC_PIO_IRQ0_INTF_SM3_RESET _u(0x0) 2618 #define PROC_PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) 2619 #define PROC_PIO_IRQ0_INTF_SM3_MSB _u(11) 2620 #define PROC_PIO_IRQ0_INTF_SM3_LSB _u(11) 2621 #define PROC_PIO_IRQ0_INTF_SM3_ACCESS "RW" 2622 // ----------------------------------------------------------------------------- 2623 // Field : PROC_PIO_IRQ0_INTF_SM2 2624 // Description : None 2625 #define PROC_PIO_IRQ0_INTF_SM2_RESET _u(0x0) 2626 #define PROC_PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) 2627 #define PROC_PIO_IRQ0_INTF_SM2_MSB _u(10) 2628 #define PROC_PIO_IRQ0_INTF_SM2_LSB _u(10) 2629 #define PROC_PIO_IRQ0_INTF_SM2_ACCESS "RW" 2630 // ----------------------------------------------------------------------------- 2631 // Field : PROC_PIO_IRQ0_INTF_SM1 2632 // Description : None 2633 #define PROC_PIO_IRQ0_INTF_SM1_RESET _u(0x0) 2634 #define PROC_PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) 2635 #define PROC_PIO_IRQ0_INTF_SM1_MSB _u(9) 2636 #define PROC_PIO_IRQ0_INTF_SM1_LSB _u(9) 2637 #define PROC_PIO_IRQ0_INTF_SM1_ACCESS "RW" 2638 // ----------------------------------------------------------------------------- 2639 // Field : PROC_PIO_IRQ0_INTF_SM0 2640 // Description : None 2641 #define PROC_PIO_IRQ0_INTF_SM0_RESET _u(0x0) 2642 #define PROC_PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) 2643 #define PROC_PIO_IRQ0_INTF_SM0_MSB _u(8) 2644 #define PROC_PIO_IRQ0_INTF_SM0_LSB _u(8) 2645 #define PROC_PIO_IRQ0_INTF_SM0_ACCESS "RW" 2646 // ----------------------------------------------------------------------------- 2647 // Field : PROC_PIO_IRQ0_INTF_SM3_TXNFULL 2648 // Description : None 2649 #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) 2650 #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) 2651 #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) 2652 #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) 2653 #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" 2654 // ----------------------------------------------------------------------------- 2655 // Field : PROC_PIO_IRQ0_INTF_SM2_TXNFULL 2656 // Description : None 2657 #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) 2658 #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) 2659 #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) 2660 #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) 2661 #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" 2662 // ----------------------------------------------------------------------------- 2663 // Field : PROC_PIO_IRQ0_INTF_SM1_TXNFULL 2664 // Description : None 2665 #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) 2666 #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) 2667 #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) 2668 #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) 2669 #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" 2670 // ----------------------------------------------------------------------------- 2671 // Field : PROC_PIO_IRQ0_INTF_SM0_TXNFULL 2672 // Description : None 2673 #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) 2674 #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) 2675 #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) 2676 #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) 2677 #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" 2678 // ----------------------------------------------------------------------------- 2679 // Field : PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY 2680 // Description : None 2681 #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) 2682 #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) 2683 #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) 2684 #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) 2685 #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" 2686 // ----------------------------------------------------------------------------- 2687 // Field : PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY 2688 // Description : None 2689 #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) 2690 #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) 2691 #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) 2692 #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) 2693 #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" 2694 // ----------------------------------------------------------------------------- 2695 // Field : PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY 2696 // Description : None 2697 #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) 2698 #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) 2699 #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) 2700 #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) 2701 #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" 2702 // ----------------------------------------------------------------------------- 2703 // Field : PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY 2704 // Description : None 2705 #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) 2706 #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) 2707 #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) 2708 #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) 2709 #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" 2710 // ============================================================================= 2711 // Register : PROC_PIO_IRQ0_INTS 2712 // Description : Interrupt status after masking & forcing for irq0 2713 #define PROC_PIO_IRQ0_INTS_OFFSET _u(0x00000158) 2714 #define PROC_PIO_IRQ0_INTS_BITS _u(0x00000fff) 2715 #define PROC_PIO_IRQ0_INTS_RESET _u(0x00000000) 2716 #define PROC_PIO_IRQ0_INTS_WIDTH _u(32) 2717 // ----------------------------------------------------------------------------- 2718 // Field : PROC_PIO_IRQ0_INTS_SM3 2719 // Description : None 2720 #define PROC_PIO_IRQ0_INTS_SM3_RESET _u(0x0) 2721 #define PROC_PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) 2722 #define PROC_PIO_IRQ0_INTS_SM3_MSB _u(11) 2723 #define PROC_PIO_IRQ0_INTS_SM3_LSB _u(11) 2724 #define PROC_PIO_IRQ0_INTS_SM3_ACCESS "RO" 2725 // ----------------------------------------------------------------------------- 2726 // Field : PROC_PIO_IRQ0_INTS_SM2 2727 // Description : None 2728 #define PROC_PIO_IRQ0_INTS_SM2_RESET _u(0x0) 2729 #define PROC_PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) 2730 #define PROC_PIO_IRQ0_INTS_SM2_MSB _u(10) 2731 #define PROC_PIO_IRQ0_INTS_SM2_LSB _u(10) 2732 #define PROC_PIO_IRQ0_INTS_SM2_ACCESS "RO" 2733 // ----------------------------------------------------------------------------- 2734 // Field : PROC_PIO_IRQ0_INTS_SM1 2735 // Description : None 2736 #define PROC_PIO_IRQ0_INTS_SM1_RESET _u(0x0) 2737 #define PROC_PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) 2738 #define PROC_PIO_IRQ0_INTS_SM1_MSB _u(9) 2739 #define PROC_PIO_IRQ0_INTS_SM1_LSB _u(9) 2740 #define PROC_PIO_IRQ0_INTS_SM1_ACCESS "RO" 2741 // ----------------------------------------------------------------------------- 2742 // Field : PROC_PIO_IRQ0_INTS_SM0 2743 // Description : None 2744 #define PROC_PIO_IRQ0_INTS_SM0_RESET _u(0x0) 2745 #define PROC_PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) 2746 #define PROC_PIO_IRQ0_INTS_SM0_MSB _u(8) 2747 #define PROC_PIO_IRQ0_INTS_SM0_LSB _u(8) 2748 #define PROC_PIO_IRQ0_INTS_SM0_ACCESS "RO" 2749 // ----------------------------------------------------------------------------- 2750 // Field : PROC_PIO_IRQ0_INTS_SM3_TXNFULL 2751 // Description : None 2752 #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) 2753 #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) 2754 #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) 2755 #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) 2756 #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" 2757 // ----------------------------------------------------------------------------- 2758 // Field : PROC_PIO_IRQ0_INTS_SM2_TXNFULL 2759 // Description : None 2760 #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) 2761 #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) 2762 #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) 2763 #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) 2764 #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" 2765 // ----------------------------------------------------------------------------- 2766 // Field : PROC_PIO_IRQ0_INTS_SM1_TXNFULL 2767 // Description : None 2768 #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) 2769 #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) 2770 #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) 2771 #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) 2772 #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" 2773 // ----------------------------------------------------------------------------- 2774 // Field : PROC_PIO_IRQ0_INTS_SM0_TXNFULL 2775 // Description : None 2776 #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) 2777 #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) 2778 #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) 2779 #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) 2780 #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" 2781 // ----------------------------------------------------------------------------- 2782 // Field : PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY 2783 // Description : None 2784 #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) 2785 #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) 2786 #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) 2787 #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) 2788 #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" 2789 // ----------------------------------------------------------------------------- 2790 // Field : PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY 2791 // Description : None 2792 #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) 2793 #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) 2794 #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) 2795 #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) 2796 #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" 2797 // ----------------------------------------------------------------------------- 2798 // Field : PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY 2799 // Description : None 2800 #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) 2801 #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) 2802 #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) 2803 #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) 2804 #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" 2805 // ----------------------------------------------------------------------------- 2806 // Field : PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY 2807 // Description : None 2808 #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) 2809 #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) 2810 #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) 2811 #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) 2812 #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" 2813 // ============================================================================= 2814 // Register : PROC_PIO_IRQ1_INTE 2815 // Description : Interrupt Enable for irq1 2816 #define PROC_PIO_IRQ1_INTE_OFFSET _u(0x0000015c) 2817 #define PROC_PIO_IRQ1_INTE_BITS _u(0x00000fff) 2818 #define PROC_PIO_IRQ1_INTE_RESET _u(0x00000000) 2819 #define PROC_PIO_IRQ1_INTE_WIDTH _u(32) 2820 // ----------------------------------------------------------------------------- 2821 // Field : PROC_PIO_IRQ1_INTE_SM3 2822 // Description : None 2823 #define PROC_PIO_IRQ1_INTE_SM3_RESET _u(0x0) 2824 #define PROC_PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) 2825 #define PROC_PIO_IRQ1_INTE_SM3_MSB _u(11) 2826 #define PROC_PIO_IRQ1_INTE_SM3_LSB _u(11) 2827 #define PROC_PIO_IRQ1_INTE_SM3_ACCESS "RW" 2828 // ----------------------------------------------------------------------------- 2829 // Field : PROC_PIO_IRQ1_INTE_SM2 2830 // Description : None 2831 #define PROC_PIO_IRQ1_INTE_SM2_RESET _u(0x0) 2832 #define PROC_PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) 2833 #define PROC_PIO_IRQ1_INTE_SM2_MSB _u(10) 2834 #define PROC_PIO_IRQ1_INTE_SM2_LSB _u(10) 2835 #define PROC_PIO_IRQ1_INTE_SM2_ACCESS "RW" 2836 // ----------------------------------------------------------------------------- 2837 // Field : PROC_PIO_IRQ1_INTE_SM1 2838 // Description : None 2839 #define PROC_PIO_IRQ1_INTE_SM1_RESET _u(0x0) 2840 #define PROC_PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) 2841 #define PROC_PIO_IRQ1_INTE_SM1_MSB _u(9) 2842 #define PROC_PIO_IRQ1_INTE_SM1_LSB _u(9) 2843 #define PROC_PIO_IRQ1_INTE_SM1_ACCESS "RW" 2844 // ----------------------------------------------------------------------------- 2845 // Field : PROC_PIO_IRQ1_INTE_SM0 2846 // Description : None 2847 #define PROC_PIO_IRQ1_INTE_SM0_RESET _u(0x0) 2848 #define PROC_PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) 2849 #define PROC_PIO_IRQ1_INTE_SM0_MSB _u(8) 2850 #define PROC_PIO_IRQ1_INTE_SM0_LSB _u(8) 2851 #define PROC_PIO_IRQ1_INTE_SM0_ACCESS "RW" 2852 // ----------------------------------------------------------------------------- 2853 // Field : PROC_PIO_IRQ1_INTE_SM3_TXNFULL 2854 // Description : None 2855 #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) 2856 #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) 2857 #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) 2858 #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) 2859 #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" 2860 // ----------------------------------------------------------------------------- 2861 // Field : PROC_PIO_IRQ1_INTE_SM2_TXNFULL 2862 // Description : None 2863 #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) 2864 #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) 2865 #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) 2866 #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) 2867 #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" 2868 // ----------------------------------------------------------------------------- 2869 // Field : PROC_PIO_IRQ1_INTE_SM1_TXNFULL 2870 // Description : None 2871 #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) 2872 #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) 2873 #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) 2874 #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) 2875 #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" 2876 // ----------------------------------------------------------------------------- 2877 // Field : PROC_PIO_IRQ1_INTE_SM0_TXNFULL 2878 // Description : None 2879 #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) 2880 #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) 2881 #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) 2882 #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) 2883 #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" 2884 // ----------------------------------------------------------------------------- 2885 // Field : PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY 2886 // Description : None 2887 #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) 2888 #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) 2889 #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) 2890 #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) 2891 #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" 2892 // ----------------------------------------------------------------------------- 2893 // Field : PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY 2894 // Description : None 2895 #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) 2896 #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) 2897 #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) 2898 #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) 2899 #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" 2900 // ----------------------------------------------------------------------------- 2901 // Field : PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY 2902 // Description : None 2903 #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) 2904 #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) 2905 #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) 2906 #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) 2907 #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" 2908 // ----------------------------------------------------------------------------- 2909 // Field : PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY 2910 // Description : None 2911 #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) 2912 #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) 2913 #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) 2914 #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) 2915 #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" 2916 // ============================================================================= 2917 // Register : PROC_PIO_IRQ1_INTF 2918 // Description : Interrupt Force for irq1 2919 #define PROC_PIO_IRQ1_INTF_OFFSET _u(0x00000160) 2920 #define PROC_PIO_IRQ1_INTF_BITS _u(0x00000fff) 2921 #define PROC_PIO_IRQ1_INTF_RESET _u(0x00000000) 2922 #define PROC_PIO_IRQ1_INTF_WIDTH _u(32) 2923 // ----------------------------------------------------------------------------- 2924 // Field : PROC_PIO_IRQ1_INTF_SM3 2925 // Description : None 2926 #define PROC_PIO_IRQ1_INTF_SM3_RESET _u(0x0) 2927 #define PROC_PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) 2928 #define PROC_PIO_IRQ1_INTF_SM3_MSB _u(11) 2929 #define PROC_PIO_IRQ1_INTF_SM3_LSB _u(11) 2930 #define PROC_PIO_IRQ1_INTF_SM3_ACCESS "RW" 2931 // ----------------------------------------------------------------------------- 2932 // Field : PROC_PIO_IRQ1_INTF_SM2 2933 // Description : None 2934 #define PROC_PIO_IRQ1_INTF_SM2_RESET _u(0x0) 2935 #define PROC_PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) 2936 #define PROC_PIO_IRQ1_INTF_SM2_MSB _u(10) 2937 #define PROC_PIO_IRQ1_INTF_SM2_LSB _u(10) 2938 #define PROC_PIO_IRQ1_INTF_SM2_ACCESS "RW" 2939 // ----------------------------------------------------------------------------- 2940 // Field : PROC_PIO_IRQ1_INTF_SM1 2941 // Description : None 2942 #define PROC_PIO_IRQ1_INTF_SM1_RESET _u(0x0) 2943 #define PROC_PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) 2944 #define PROC_PIO_IRQ1_INTF_SM1_MSB _u(9) 2945 #define PROC_PIO_IRQ1_INTF_SM1_LSB _u(9) 2946 #define PROC_PIO_IRQ1_INTF_SM1_ACCESS "RW" 2947 // ----------------------------------------------------------------------------- 2948 // Field : PROC_PIO_IRQ1_INTF_SM0 2949 // Description : None 2950 #define PROC_PIO_IRQ1_INTF_SM0_RESET _u(0x0) 2951 #define PROC_PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) 2952 #define PROC_PIO_IRQ1_INTF_SM0_MSB _u(8) 2953 #define PROC_PIO_IRQ1_INTF_SM0_LSB _u(8) 2954 #define PROC_PIO_IRQ1_INTF_SM0_ACCESS "RW" 2955 // ----------------------------------------------------------------------------- 2956 // Field : PROC_PIO_IRQ1_INTF_SM3_TXNFULL 2957 // Description : None 2958 #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) 2959 #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) 2960 #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) 2961 #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) 2962 #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" 2963 // ----------------------------------------------------------------------------- 2964 // Field : PROC_PIO_IRQ1_INTF_SM2_TXNFULL 2965 // Description : None 2966 #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) 2967 #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) 2968 #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) 2969 #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) 2970 #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" 2971 // ----------------------------------------------------------------------------- 2972 // Field : PROC_PIO_IRQ1_INTF_SM1_TXNFULL 2973 // Description : None 2974 #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) 2975 #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) 2976 #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) 2977 #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) 2978 #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" 2979 // ----------------------------------------------------------------------------- 2980 // Field : PROC_PIO_IRQ1_INTF_SM0_TXNFULL 2981 // Description : None 2982 #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) 2983 #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) 2984 #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) 2985 #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) 2986 #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" 2987 // ----------------------------------------------------------------------------- 2988 // Field : PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY 2989 // Description : None 2990 #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) 2991 #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) 2992 #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) 2993 #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) 2994 #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" 2995 // ----------------------------------------------------------------------------- 2996 // Field : PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY 2997 // Description : None 2998 #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) 2999 #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) 3000 #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) 3001 #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) 3002 #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" 3003 // ----------------------------------------------------------------------------- 3004 // Field : PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY 3005 // Description : None 3006 #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) 3007 #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) 3008 #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) 3009 #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) 3010 #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" 3011 // ----------------------------------------------------------------------------- 3012 // Field : PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY 3013 // Description : None 3014 #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) 3015 #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) 3016 #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) 3017 #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) 3018 #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" 3019 // ============================================================================= 3020 // Register : PROC_PIO_IRQ1_INTS 3021 // Description : Interrupt status after masking & forcing for irq1 3022 #define PROC_PIO_IRQ1_INTS_OFFSET _u(0x00000164) 3023 #define PROC_PIO_IRQ1_INTS_BITS _u(0x00000fff) 3024 #define PROC_PIO_IRQ1_INTS_RESET _u(0x00000000) 3025 #define PROC_PIO_IRQ1_INTS_WIDTH _u(32) 3026 // ----------------------------------------------------------------------------- 3027 // Field : PROC_PIO_IRQ1_INTS_SM3 3028 // Description : None 3029 #define PROC_PIO_IRQ1_INTS_SM3_RESET _u(0x0) 3030 #define PROC_PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) 3031 #define PROC_PIO_IRQ1_INTS_SM3_MSB _u(11) 3032 #define PROC_PIO_IRQ1_INTS_SM3_LSB _u(11) 3033 #define PROC_PIO_IRQ1_INTS_SM3_ACCESS "RO" 3034 // ----------------------------------------------------------------------------- 3035 // Field : PROC_PIO_IRQ1_INTS_SM2 3036 // Description : None 3037 #define PROC_PIO_IRQ1_INTS_SM2_RESET _u(0x0) 3038 #define PROC_PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) 3039 #define PROC_PIO_IRQ1_INTS_SM2_MSB _u(10) 3040 #define PROC_PIO_IRQ1_INTS_SM2_LSB _u(10) 3041 #define PROC_PIO_IRQ1_INTS_SM2_ACCESS "RO" 3042 // ----------------------------------------------------------------------------- 3043 // Field : PROC_PIO_IRQ1_INTS_SM1 3044 // Description : None 3045 #define PROC_PIO_IRQ1_INTS_SM1_RESET _u(0x0) 3046 #define PROC_PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) 3047 #define PROC_PIO_IRQ1_INTS_SM1_MSB _u(9) 3048 #define PROC_PIO_IRQ1_INTS_SM1_LSB _u(9) 3049 #define PROC_PIO_IRQ1_INTS_SM1_ACCESS "RO" 3050 // ----------------------------------------------------------------------------- 3051 // Field : PROC_PIO_IRQ1_INTS_SM0 3052 // Description : None 3053 #define PROC_PIO_IRQ1_INTS_SM0_RESET _u(0x0) 3054 #define PROC_PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) 3055 #define PROC_PIO_IRQ1_INTS_SM0_MSB _u(8) 3056 #define PROC_PIO_IRQ1_INTS_SM0_LSB _u(8) 3057 #define PROC_PIO_IRQ1_INTS_SM0_ACCESS "RO" 3058 // ----------------------------------------------------------------------------- 3059 // Field : PROC_PIO_IRQ1_INTS_SM3_TXNFULL 3060 // Description : None 3061 #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) 3062 #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) 3063 #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) 3064 #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) 3065 #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" 3066 // ----------------------------------------------------------------------------- 3067 // Field : PROC_PIO_IRQ1_INTS_SM2_TXNFULL 3068 // Description : None 3069 #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) 3070 #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) 3071 #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) 3072 #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) 3073 #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" 3074 // ----------------------------------------------------------------------------- 3075 // Field : PROC_PIO_IRQ1_INTS_SM1_TXNFULL 3076 // Description : None 3077 #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) 3078 #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) 3079 #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) 3080 #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) 3081 #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" 3082 // ----------------------------------------------------------------------------- 3083 // Field : PROC_PIO_IRQ1_INTS_SM0_TXNFULL 3084 // Description : None 3085 #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) 3086 #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) 3087 #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) 3088 #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) 3089 #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" 3090 // ----------------------------------------------------------------------------- 3091 // Field : PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY 3092 // Description : None 3093 #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) 3094 #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) 3095 #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) 3096 #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) 3097 #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" 3098 // ----------------------------------------------------------------------------- 3099 // Field : PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY 3100 // Description : None 3101 #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) 3102 #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) 3103 #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) 3104 #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) 3105 #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" 3106 // ----------------------------------------------------------------------------- 3107 // Field : PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY 3108 // Description : None 3109 #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) 3110 #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) 3111 #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) 3112 #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) 3113 #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" 3114 // ----------------------------------------------------------------------------- 3115 // Field : PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY 3116 // Description : None 3117 #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) 3118 #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) 3119 #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) 3120 #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) 3121 #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" 3122 // ============================================================================= 3123 // Register : PROC_PIO_BLOCK_ID 3124 // Description : Block Identifier 3125 // Hexadecimal representation of "pio2" 3126 #define PROC_PIO_BLOCK_ID_OFFSET _u(0x00000168) 3127 #define PROC_PIO_BLOCK_ID_BITS _u(0xffffffff) 3128 #define PROC_PIO_BLOCK_ID_RESET _u(0x70696f32) 3129 #define PROC_PIO_BLOCK_ID_WIDTH _u(32) 3130 #define PROC_PIO_BLOCK_ID_MSB _u(31) 3131 #define PROC_PIO_BLOCK_ID_LSB _u(0) 3132 #define PROC_PIO_BLOCK_ID_ACCESS "RO" 3133 // ============================================================================= 3134 // Register : PROC_PIO_INSTANCE_ID 3135 // Description : Block Instance Identifier 3136 #define PROC_PIO_INSTANCE_ID_OFFSET _u(0x0000016c) 3137 #define PROC_PIO_INSTANCE_ID_BITS _u(0x0000000f) 3138 #define PROC_PIO_INSTANCE_ID_RESET _u(0x00000000) 3139 #define PROC_PIO_INSTANCE_ID_WIDTH _u(32) 3140 #define PROC_PIO_INSTANCE_ID_MSB _u(3) 3141 #define PROC_PIO_INSTANCE_ID_LSB _u(0) 3142 #define PROC_PIO_INSTANCE_ID_ACCESS "RO" 3143 // ============================================================================= 3144 // Register : PROC_PIO_RSTSEQ_AUTO 3145 // Description : None 3146 #define PROC_PIO_RSTSEQ_AUTO_OFFSET _u(0x00000170) 3147 #define PROC_PIO_RSTSEQ_AUTO_BITS _u(0x00000001) 3148 #define PROC_PIO_RSTSEQ_AUTO_RESET _u(0x00000001) 3149 #define PROC_PIO_RSTSEQ_AUTO_WIDTH _u(32) 3150 // ----------------------------------------------------------------------------- 3151 // Field : PROC_PIO_RSTSEQ_AUTO_BUSADAPTER 3152 // Description : 1 = reset is controlled by the sequencer 3153 // 0 = reset is controlled by rstseq_ctrl 3154 #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_RESET _u(0x1) 3155 #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_BITS _u(0x00000001) 3156 #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_MSB _u(0) 3157 #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_LSB _u(0) 3158 #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW" 3159 // ============================================================================= 3160 // Register : PROC_PIO_RSTSEQ_PARALLEL 3161 // Description : None 3162 #define PROC_PIO_RSTSEQ_PARALLEL_OFFSET _u(0x00000174) 3163 #define PROC_PIO_RSTSEQ_PARALLEL_BITS _u(0x00000001) 3164 #define PROC_PIO_RSTSEQ_PARALLEL_RESET _u(0x00000000) 3165 #define PROC_PIO_RSTSEQ_PARALLEL_WIDTH _u(32) 3166 // ----------------------------------------------------------------------------- 3167 // Field : PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER 3168 // Description : Is this reset parallel (i.e. not part of the sequence) 3169 #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_RESET _u(0x0) 3170 #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_BITS _u(0x00000001) 3171 #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_MSB _u(0) 3172 #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_LSB _u(0) 3173 #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO" 3174 // ============================================================================= 3175 // Register : PROC_PIO_RSTSEQ_CTRL 3176 // Description : None 3177 #define PROC_PIO_RSTSEQ_CTRL_OFFSET _u(0x00000178) 3178 #define PROC_PIO_RSTSEQ_CTRL_BITS _u(0x00000001) 3179 #define PROC_PIO_RSTSEQ_CTRL_RESET _u(0x00000000) 3180 #define PROC_PIO_RSTSEQ_CTRL_WIDTH _u(32) 3181 // ----------------------------------------------------------------------------- 3182 // Field : PROC_PIO_RSTSEQ_CTRL_BUSADAPTER 3183 // Description : 1 = keep the reset asserted 3184 // 0 = keep the reset deasserted 3185 // This is ignored if rstseq_auto=1 3186 #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_RESET _u(0x0) 3187 #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_BITS _u(0x00000001) 3188 #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_MSB _u(0) 3189 #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_LSB _u(0) 3190 #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW" 3191 // ============================================================================= 3192 // Register : PROC_PIO_RSTSEQ_TRIG 3193 // Description : None 3194 #define PROC_PIO_RSTSEQ_TRIG_OFFSET _u(0x0000017c) 3195 #define PROC_PIO_RSTSEQ_TRIG_BITS _u(0x00000001) 3196 #define PROC_PIO_RSTSEQ_TRIG_RESET _u(0x00000000) 3197 #define PROC_PIO_RSTSEQ_TRIG_WIDTH _u(32) 3198 // ----------------------------------------------------------------------------- 3199 // Field : PROC_PIO_RSTSEQ_TRIG_BUSADAPTER 3200 // Description : Pulses the reset output 3201 #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_RESET _u(0x0) 3202 #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_BITS _u(0x00000001) 3203 #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_MSB _u(0) 3204 #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_LSB _u(0) 3205 #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC" 3206 // ============================================================================= 3207 // Register : PROC_PIO_RSTSEQ_DONE 3208 // Description : None 3209 #define PROC_PIO_RSTSEQ_DONE_OFFSET _u(0x00000180) 3210 #define PROC_PIO_RSTSEQ_DONE_BITS _u(0x00000001) 3211 #define PROC_PIO_RSTSEQ_DONE_RESET _u(0x00000000) 3212 #define PROC_PIO_RSTSEQ_DONE_WIDTH _u(32) 3213 // ----------------------------------------------------------------------------- 3214 // Field : PROC_PIO_RSTSEQ_DONE_BUSADAPTER 3215 // Description : Indicates the current state of the reset 3216 #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_RESET _u(0x0) 3217 #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_BITS _u(0x00000001) 3218 #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_MSB _u(0) 3219 #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_LSB _u(0) 3220 #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO" 3221 // ============================================================================= 3222 #endif // HARDWARE_REGS_PROC_PIO_DEFINED