1  /* SPDX-License-Identifier: GPL-2.0-only */
  2  
  3  #include <device/pci.h>
  4  #include <cpu/x86/mp.h>
  5  #include <cpu/x86/msr.h>
  6  #include <cpu/intel/smm_reloc.h>
  7  #include <cpu/intel/turbo.h>
  8  #include <cpu/intel/common/common.h>
  9  #include <fsp/api.h>
 10  #include <intelblocks/cpulib.h>
 11  #include <intelblocks/mp_init.h>
 12  #include <intelblocks/msr.h>
 13  #include <soc/cpu.h>
 14  #include <soc/msr.h>
 15  #include <soc/pci_devs.h>
 16  #include <soc/soc_chip.h>
 17  #include <static.h>
 18  #include <types.h>
 19  
 20  bool cpu_soc_is_in_untrusted_mode(void)
 21  {
 22  	msr_t msr;
 23  
 24  	msr = rdmsr(MSR_BIOS_DONE);
 25  	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 26  }
 27  
 28  void cpu_soc_bios_done(void)
 29  {
 30  	msr_t msr;
 31  
 32  	msr = rdmsr(MSR_BIOS_DONE);
 33  	msr.lo |= ENABLE_IA_UNTRUSTED;
 34  	wrmsr(MSR_BIOS_DONE, msr);
 35  }
 36  
 37  static void soc_fsp_load(void)
 38  {
 39  	fsps_load();
 40  }
 41  
 42  static void configure_misc(void)
 43  {
 44  	msr_t msr;
 45  
 46  	config_t *conf = config_of_soc();
 47  
 48  	msr = rdmsr(IA32_MISC_ENABLE);
 49  	msr.lo |= (1 << 0);	/* Fast String enable */
 50  	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
 51  	wrmsr(IA32_MISC_ENABLE, msr);
 52  
 53  	/* Set EIST status */
 54  	cpu_set_eist(conf->eist_enable);
 55  
 56  	/* Disable Thermal interrupts */
 57  	msr.lo = 0;
 58  	msr.hi = 0;
 59  	wrmsr(IA32_THERM_INTERRUPT, msr);
 60  
 61  	/* Enable package critical interrupt only */
 62  	msr.lo = 1 << 4;
 63  	msr.hi = 0;
 64  	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
 65  
 66  	/* Enable PROCHOT */
 67  	msr = rdmsr(MSR_POWER_CTL);
 68  	msr.lo |= (1 << 0);	/* Enable Bi-directional PROCHOT as an input */
 69  	msr.lo |= (1 << 23);	/* Lock it */
 70  	wrmsr(MSR_POWER_CTL, msr);
 71  }
 72  
 73  /* All CPUs including BSP will run the following function. */
 74  void soc_core_init(struct device *cpu)
 75  {
 76  	/* Clear out pending MCEs */
 77  	/* TODO(adurbin): This should only be done on a cold boot. Also, some
 78  	 * of these banks are core vs package scope. For now every CPU clears
 79  	 * every bank. */
 80  	mca_configure();
 81  
 82  	enable_lapic_tpr();
 83  
 84  	/* Configure Enhanced SpeedStep and Thermal Sensors */
 85  	configure_misc();
 86  
 87  	enable_pm_timer_emulation();
 88  
 89  	/* Enable Direct Cache Access */
 90  	configure_dca_cap();
 91  
 92  	/* Set energy policy */
 93  	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 94  
 95  	/* Enable Turbo */
 96  	enable_turbo();
 97  }
 98  
 99  static void per_cpu_smm_trigger(void)
100  {
101  	/* Relocate the SMM handler. */
102  	smm_relocate();
103  }
104  
105  static void post_mp_init(void)
106  {
107  	/* Set Max Ratio */
108  	cpu_set_max_ratio();
109  
110  	/*
111  	 * 1. Now that all APs have been relocated as well as the BSP let SMIs
112  	 * start flowing.
113  	 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
114  	 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
115  	 */
116  	global_smi_enable_no_pwrbtn();
117  }
118  
119  static const struct mp_ops mp_ops = {
120  	/*
121  	 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
122  	 * that are set prior to ramstage.
123  	 * Real MTRRs programming are being done after resource allocation.
124  	 */
125  	.pre_mp_init = soc_fsp_load,
126  	.get_cpu_count = get_cpu_count,
127  	.get_smm_info = smm_info,
128  	.get_microcode_info = get_microcode_info,
129  	.pre_mp_smm_init = smm_initialize,
130  	.per_cpu_smm_trigger = per_cpu_smm_trigger,
131  	.relocation_handler = smm_relocation_handler,
132  	.post_mp_init = post_mp_init,
133  };
134  
135  void mp_init_cpus(struct bus *cpu_bus)
136  {
137  	/* TODO: Handle mp_init_with_smm failure? */
138  	mp_init_with_smm(cpu_bus, &mp_ops);
139  
140  	/* Thermal throttle activation offset */
141  	configure_tcc_thermal_target();
142  }