1  /* SPDX-License-Identifier: GPL-2.0-only */
  2  
  3  #include <bootstate.h>
  4  #include <console/console.h>
  5  #include <device/mmio.h>
  6  #include <device/device.h>
  7  #include <intelblocks/acpi.h>
  8  #include <intelblocks/pmc.h>
  9  #include <intelblocks/pmclib.h>
 10  #include <intelblocks/rtc.h>
 11  #include <soc/pci_devs.h>
 12  #include <soc/pm.h>
 13  #include <soc/soc_chip.h>
 14  #include <static.h>
 15  
 16  static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
 17  {
 18  	uint32_t reg;
 19  	uint8_t *pmcbase = pmc_mmio_regs();
 20  
 21  	printk(BIOS_DEBUG, "%sabling Deep S%c\n",
 22  		enable ? "En" : "Dis", sx + '0');
 23  	reg = read32(pmcbase + offset);
 24  	if (enable)
 25  		reg |= mask;
 26  	else
 27  		reg &= ~mask;
 28  	write32(pmcbase + offset, reg);
 29  }
 30  
 31  static void config_deep_s5(int on_ac, int on_dc)
 32  {
 33  	/* Treat S4 the same as S5. */
 34  	config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
 35  	config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
 36  	config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
 37  	config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
 38  }
 39  
 40  static void config_deep_s3(int on_ac, int on_dc)
 41  {
 42  	config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
 43  	config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
 44  }
 45  
 46  static void config_deep_sx(uint32_t deepsx_config)
 47  {
 48  	uint32_t reg;
 49  	uint8_t *pmcbase = pmc_mmio_regs();
 50  
 51  	reg = read32(pmcbase + DSX_CFG);
 52  	reg &= ~DSX_CFG_MASK;
 53  	reg |= deepsx_config;
 54  	write32(pmcbase + DSX_CFG, reg);
 55  }
 56  
 57  static void soc_pmc_enable(struct device *dev)
 58  {
 59  	const config_t *config = config_of_soc();
 60  
 61  	rtc_init();
 62  
 63  	pmc_set_power_failure_state(true);
 64  	pmc_gpe_init();
 65  
 66  	config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
 67  	config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
 68  	config_deep_sx(config->deep_sx_config);
 69  }
 70  
 71  static void soc_pmc_read_resources(struct device *dev)
 72  {
 73  	struct resource *res;
 74  
 75  	mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
 76  
 77  	res = new_resource(dev, 1);
 78  	res->base = (resource_t)ACPI_BASE_ADDRESS;
 79  	res->size = (resource_t)ACPI_BASE_SIZE;
 80  	res->limit = res->base + res->size - 1;
 81  	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 82  }
 83  
 84  static void soc_pmc_init(struct device *dev)
 85  {
 86  	/*
 87  	 * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
 88  	 * to ensure the ordering does not break the assumptions that other
 89  	 * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
 90  	 * ACPI mode, other drivers may take different actions based on this
 91  	 * (e.g. Chrome EC will flush any pending hostevent bits). Because
 92  	 * JSL has its PMC device available for device_operations, it can be
 93  	 * done from the "ops->init" callback.
 94  	 */
 95  	pmc_set_acpi_mode();
 96  
 97  	/*
 98  	 * Disable ACPI PM timer based on Kconfig
 99  	 *
100  	 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
101  	 * Disabling ACPI PM timer also switches off TCO
102  	 */
103  	if (!CONFIG(USE_PM_ACPI_TIMER))
104  		setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
105  }
106  
107  static void pm1_enable_pwrbtn_smi(void *unused)
108  {
109  	/* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
110  	pmc_update_pm1_enable(PWRBTN_EN);
111  }
112  
113  BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
114  
115  static void pmc_fill_ssdt(const struct device *dev)
116  {
117  	if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
118  		generate_acpi_power_engine();
119  }
120  
121  /*
122   * `pmc_final` function is native implementation of equivalent events performed by
123   * each FSP NotifyPhase() API invocations.
124   *
125   *
126   * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
127   *
128   * Perform the PMCON status bit clear operation from `.final`
129   * to cover any such chances where later boot stage requested a global
130   * reset and PMCON status bit remains set.
131   */
132  static void pmc_final(struct device *dev)
133  {
134  	pmc_clear_pmcon_sts();
135  }
136  
137  struct device_operations pmc_ops = {
138  	.read_resources		= soc_pmc_read_resources,
139  	.set_resources		= noop_set_resources,
140  	.init			= soc_pmc_init,
141  	.enable			= soc_pmc_enable,
142  #if CONFIG(HAVE_ACPI_TABLES)
143  	.acpi_fill_ssdt		= pmc_fill_ssdt,
144  #endif
145  	.final			= pmc_final,
146  };