1  _start:
 2      # Configure PMP: allow all access for S-mode
 3      li x1, 0x1F
 4      csrw pmpcfg0, x1
 5      li x1, -1
 6      csrw pmpaddr0, x1
 7  
 8      li x31, 0xde
 9  
10      la x1, machine_trap
11      csrw mtvec, x1
12  
13      la x1, supervisor_trap
14      csrw stvec, x1
15  
16      li x1, 1 << 17 # delegate custom level interrupt to supervisor mode
17      csrw mideleg, x1
18  
19      li x1, 1 << 17
20      csrw sie, x1
21  
22      # Set MPP to supervisor and transfer via MRET.
23      li x1, 0b11 << 11
24      csrc mstatus, x1
25      li x1, 0b01 << 11
26      csrs mstatus, x1
27  
28      la x1, s_mode_main
29      csrw mepc, x1
30      mret
31  
32  s_mode_main:
33      csrr x2, 0x8ff # custom testbench CSR - current privilege mode
34      li x3, 1
35      bne x2, x3, fail
36  
37      li x3, 1
38      csrsi sstatus, 0x2 # set sstatus.SIE
39  
40  wait_for_interrupt:
41      beq x7, x3, after_interrupt
42      j wait_for_interrupt
43  
44  after_interrupt:
45      csrr x10, sstatus
46      andi x11, x10, 0x2
47      beqz x11, fail
48  
49      li x5, 1
50      j pass
51  
52  supervisor_trap:
53      addi x7, x7, 1
54  
55      csrr x8, scause
56      li x9, 0x80000011
57      bne x8, x9, fail
58  
59      # During trap handling: SIE must be cleared and SPIE should be set.
60      csrr x10, sstatus
61      andi x11, x10, 0x2
62      bnez x11, fail
63  
64      andi x12, x10, 0x20
65      beqz x12, fail
66  
67      sret
68  
69  machine_trap:
70      # M-mode trap handler must not fire in this test (interrupt is delegated)
71      li x31, 0xae
72  
73  fail:
74      j fail
75  
76  pass:
77      j pass