1  .include "init_regs.s"
 2  
 3  _start:
 4      INIT_REGS_LOAD
 5  
 6      li x1, 0x100 # set handler vector
 7      csrw mtvec, x1
 8      li x1, 0x10000 # enable custom interrupt 0
 9      csrw mie, x1
10      csrsi mstatus, 0x8 # machine interrupt enable
11      csrr x29, mstatus
12      li x3, 0
13  loop:
14      wfi
15      beq x2, x3, loop
16  infloop:
17      j infloop
18  
19  handler:
20      addi x30, x30, 1
21      addi x27, x27, 1
22      li x1, 0x10000
23      csrc mip, x1 # clear edge reported interrupt
24      beq x2, x3, skip
25      addi x3, x3, 1
26  skip:
27      mret
28  
29  .org 0x100
30      j handler
31  
32  INIT_REGS_ALLOCATION