1  Before:
 2    runtime ale_linters/verilog/verilator.vim
 3  
 4  After:
 5    call ale#linter#Reset()
 6  
 7  Execute (The verilator handler should parse legacy messages with only line numbers):
 8    AssertEqual
 9    \ [
10    \   {
11    \     'lnum': 3,
12    \     'type': 'E',
13    \     'text': 'syntax error, unexpected IDENTIFIER',
14    \     'filename': 'foo.v'
15    \   },
16    \   {
17    \     'lnum': 10,
18    \     'type': 'W',
19    \     'text': 'Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
20    \     'filename': 'bar.v'
21    \   },
22    \ ],
23    \ ale_linters#verilog#verilator#Handle(bufnr(''), [
24    \ '%Error: foo.v:3: syntax error, unexpected IDENTIFIER',
25    \ '%Warning-BLKSEQ: bar.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
26    \ ])
27  
28  Execute (The verilator handler should parse new format messages with line and column numbers):
29    AssertEqual
30    \ [
31    \   {
32    \     'lnum': 3,
33    \     'col' : 1,
34    \     'type': 'E',
35    \     'text': 'syntax error, unexpected endmodule, expecting ;',
36    \     'filename': 'bar.v'
37    \   },
38    \   {
39    \     'lnum': 4,
40    \     'col' : 6,
41    \     'type': 'W',
42    \     'text': 'Signal is not used: r',
43    \     'filename': 'foo.v'
44    \   },
45    \ ],
46    \ ale_linters#verilog#verilator#Handle(bufnr(''), [
47    \ '%Error: bar.v:3:1: syntax error, unexpected endmodule, expecting ;',
48    \ '%Warning-UNUSED: foo.v:4:6: Signal is not used: r',
49    \ ])