/ timestamp.vhd
timestamp.vhd
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 6 -- 7 -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics 8 -- http://www.mesanet.com 9 -- 10 -- This program is is licensed under a disjunctive dual license giving you 11 -- the choice of one of the two following sets of free software/open source 12 -- licensing terms: 13 -- 14 -- * GNU General Public License (GPL), version 2.0 or later 15 -- * 3-clause BSD License 16 -- 17 -- 18 -- The GNU GPL License: 19 -- 20 -- This program is free software; you can redistribute it and/or modify 21 -- it under the terms of the GNU General Public License as published by 22 -- the Free Software Foundation; either version 2 of the License, or 23 -- (at your option) any later version. 24 -- 25 -- This program is distributed in the hope that it will be useful, 26 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 27 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 -- GNU General Public License for more details. 29 -- 30 -- You should have received a copy of the GNU General Public License 31 -- along with this program; if not, write to the Free Software 32 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 33 -- 34 -- 35 -- The 3-clause BSD License: 36 -- 37 -- Redistribution and use in source and binary forms, with or without 38 -- modification, are permitted provided that the following conditions 39 -- are met: 40 -- 41 -- * Redistributions of source code must retain the above copyright 42 -- notice, this list of conditions and the following disclaimer. 43 -- 44 -- * Redistributions in binary form must reproduce the above 45 -- copyright notice, this list of conditions and the following 46 -- disclaimer in the documentation and/or other materials 47 -- provided with the distribution. 48 -- 49 -- * Neither the name of Mesa Electronics nor the names of its 50 -- contributors may be used to endorse or promote products 51 -- derived from this software without specific prior written 52 -- permission. 53 -- 54 -- 55 -- Disclaimer: 56 -- 57 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 58 -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 59 -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 60 -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 61 -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 62 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 63 -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 64 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 65 -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 -- POSSIBILITY OF SUCH DAMAGE. 69 -- 70 71 72 entity timestamp is 73 Port ( ibus : in std_logic_vector(15 downto 0); 74 obus : out std_logic_vector(15 downto 0); 75 loadtsdiv : in std_logic; 76 readts : in std_logic; 77 readtsdiv : in std_logic; 78 tscount : out std_logic_vector (15 downto 0); 79 clk : in std_logic); 80 end timestamp; 81 82 architecture Behavioral of timestamp is 83 84 signal counter: std_logic_vector (15 downto 0); 85 signal div: std_logic_vector(15 downto 0); 86 alias divmsb: std_logic is div(15); 87 signal divlatch: std_logic_vector (15 downto 0); 88 89 begin 90 91 atimestamp: process (clk,readts, counter, readtsdiv, divlatch) 92 begin 93 if rising_edge(clk) then 94 div <= div -1; 95 if divmsb = '1' then 96 div <= divlatch; 97 counter <= counter + 1; 98 end if; 99 if loadtsdiv = '1' then 100 divlatch <= ibus; 101 end if; 102 end if; -- clk 103 obus <= (others => 'Z'); 104 if readts = '1' then 105 obus <= counter; 106 end if; 107 if readtsdiv = '1' then 108 obus <= divlatch; 109 end if; 110 tscount <= counter; 111 end process; 112 113 end Behavioral;