amdfwtool.h
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _AMD_FW_TOOL_H_ 4 #define _AMD_FW_TOOL_H_ 5 6 #include <commonlib/bsd/compiler.h> 7 #include <commonlib/bsd/helpers.h> 8 #include <openssl/sha.h> 9 #include <stdint.h> 10 #include <stdbool.h> 11 12 #define ERASE_ALIGNMENT 0x1000U 13 #define TABLE_ALIGNMENT 0x1000U 14 #define TABLE_L2_SIZE_MAX 0x400U 15 #define BLOB_ALIGNMENT 0x100U 16 #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) 17 #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) 18 19 enum platform { 20 PLATFORM_UNKNOWN, 21 PLATFORM_CARRIZO, 22 PLATFORM_STONEYRIDGE, 23 PLATFORM_RAVEN, 24 PLATFORM_PICASSO, 25 PLATFORM_RENOIR, 26 PLATFORM_CEZANNE, 27 PLATFORM_MENDOCINO, 28 PLATFORM_LUCIENNE, 29 PLATFORM_PHOENIX, 30 PLATFORM_GLINDA, 31 PLATFORM_GENOA, 32 }; 33 34 typedef enum _amd_fw_type { 35 AMD_FW_PSP_PUBKEY = 0x00, 36 AMD_FW_PSP_BOOTLOADER = 0x01, 37 AMD_FW_PSP_SECURED_OS = 0x02, 38 AMD_FW_PSP_RECOVERY = 0x03, 39 AMD_FW_PSP_NVRAM = 0x04, 40 AMD_FW_PSP_RTM_PUBKEY = 0x05, 41 AMD_FW_PSP_SMU_FIRMWARE = 0x08, 42 AMD_FW_PSP_SECURED_DEBUG = 0x09, 43 AMD_FW_ABL_PUBKEY = 0x0a, 44 AMD_PSP_FUSE_CHAIN = 0x0b, 45 AMD_FW_PSP_TRUSTLETS = 0x0c, 46 AMD_FW_PSP_TRUSTLETKEY = 0x0d, 47 AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, 48 AMD_DEBUG_UNLOCK = 0x13, 49 AMD_BOOT_DRIVER = 0x1b, 50 AMD_SOC_DRIVER = 0x1c, 51 AMD_DEBUG_DRIVER = 0x1d, 52 AMD_INTERFACE_DRIVER = 0x1f, 53 AMD_HW_IPCFG = 0x20, 54 AMD_WRAPPED_IKEK = 0x21, 55 AMD_TOKEN_UNLOCK = 0x22, 56 AMD_SEC_GASKET = 0x24, 57 AMD_MP2_FW = 0x25, 58 AMD_DRIVER_ENTRIES = 0x28, 59 AMD_FW_KVM_IMAGE = 0x29, 60 AMD_FW_MP5 = 0x2a, 61 AMD_S0I3_DRIVER = 0x2d, 62 AMD_ABL0 = 0x30, 63 AMD_ABL1 = 0x31, 64 AMD_ABL2 = 0x32, 65 AMD_ABL3 = 0x33, 66 AMD_ABL4 = 0x34, 67 AMD_ABL5 = 0x35, 68 AMD_ABL6 = 0x36, 69 AMD_ABL7 = 0x37, 70 AMD_SEV_DATA = 0x38, 71 AMD_SEV_CODE = 0x39, 72 AMD_FW_PSP_WHITELIST = 0x3a, 73 AMD_VBIOS_BTLOADER = 0x3c, 74 AMD_FW_L2_PTR = 0x40, 75 AMD_FW_DXIO = 0x42, 76 AMD_FW_USB_PHY = 0x44, 77 AMD_FW_TOS_SEC_POLICY = 0x45, 78 AMD_FW_DRTM_TA = 0x47, 79 AMD_FW_RECOVERYAB_A = 0x48, 80 AMD_FW_RECOVERYAB_B = 0x4A, 81 AMD_FW_BIOS_TABLE = 0x49, 82 AMD_FW_KEYDB_BL = 0x50, 83 AMD_FW_KEYDB_TOS = 0x51, 84 AMD_FW_PSP_VERSTAGE = 0x52, 85 AMD_FW_VERSTAGE_SIG = 0x53, 86 AMD_RPMC_NVRAM = 0x54, 87 AMD_FW_SPL = 0x55, 88 AMD_FW_DMCU_ERAM = 0x58, 89 AMD_FW_DMCU_ISR = 0x59, 90 AMD_FW_MSMU = 0x5a, 91 AMD_FW_SPIROM_CFG = 0x5c, 92 AMD_FW_MPIO = 0x5d, 93 AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ 94 AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ 95 AMD_FW_DMCUB = 0x71, 96 AMD_FW_PSP_BOOTLOADER_AB = 0x73, 97 AMD_RIB = 0x76, 98 AMD_FW_AMF_SRAM = 0x85, 99 AMD_FW_AMF_DRAM = 0x86, 100 AMD_FW_AMF_WLAN = 0x88, 101 AMD_FW_AMF_MFD = 0x89, 102 AMD_FW_MPDMA_TF = 0x8c, 103 AMD_TA_IKEK = 0x8d, 104 AMD_FW_MPCCX = 0x90, 105 AMD_FW_GMI3_PHY = 0x91, 106 AMD_FW_MPDMA_PM = 0x92, 107 AMD_FW_LSDMA = 0x94, 108 AMD_FW_C20_MP = 0x95, 109 AMD_FW_FCFG_TABLE = 0x98, 110 AMD_FW_MINIMSMU = 0x9a, 111 AMD_FW_SRAM_FW_EXT = 0x9d, 112 AMD_FW_UMSMU = 0xa2, 113 AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ 114 AMD_FW_GEC, 115 AMD_FW_XHCI, 116 AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ 117 AMD_FW_SKIP /* This is for non-applicable options. */ 118 } amd_fw_type; 119 120 typedef enum _amd_bios_type { 121 AMD_BIOS_RTM_PUBKEY = 0x05, 122 AMD_BIOS_SIG = 0x07, 123 AMD_BIOS_APCB = 0x60, 124 AMD_BIOS_APOB = 0x61, 125 AMD_BIOS_BIN = 0x62, 126 AMD_BIOS_APOB_NV = 0x63, 127 AMD_BIOS_PMUI = 0x64, 128 AMD_BIOS_PMUD = 0x65, 129 AMD_BIOS_UCODE = 0x66, 130 AMD_BIOS_APCB_BK = 0x68, 131 AMD_BIOS_EARLY_VGA = 0x69, 132 AMD_BIOS_MP2_CFG = 0x6a, 133 AMD_BIOS_PSP_SHARED_MEM = 0x6b, 134 AMD_BIOS_L2_PTR = 0x70, 135 AMD_BIOS_INVALID, 136 AMD_BIOS_SKIP 137 } amd_bios_type; 138 139 typedef enum _amd_addr_mode { 140 AMD_ADDR_PHYSICAL = 0, /* Physical address */ 141 AMD_ADDR_REL_BIOS, /* Relative to beginning of image */ 142 AMD_ADDR_REL_TAB, /* Relative to table */ 143 AMD_ADDR_REL_SLOT, /* Relative to slot */ 144 } amd_addr_mode; 145 146 struct second_gen_efs { /* todo: expand for Server products */ 147 uint32_t gen:1; /* Client products only use bit 0 */ 148 uint32_t reserved:31; 149 } __attribute__((packed)); 150 151 #define EFS_SECOND_GEN 0 152 #define EFS_BEFORE_SECOND_GEN 1 153 154 typedef struct _embedded_firmware { 155 uint32_t signature; /* 0x55aa55aa */ 156 uint32_t imc_entry; 157 uint32_t gec_entry; 158 uint32_t xhci_entry; 159 uint32_t psp_directory; 160 uint32_t new_psp_directory; /* also used as combo_psp_directory */ 161 uint32_t bios0_entry; /* todo: add way to select correct entry */ 162 uint32_t bios1_entry; 163 uint32_t bios2_entry; 164 struct second_gen_efs efs_gen; 165 uint32_t bios3_entry; 166 uint32_t psp_bak_directory; 167 uint32_t promontory_fw_ptr; 168 uint32_t lp_promontory_fw_ptr; 169 uint32_t reserved_38h; 170 uint32_t reserved_3Ch; 171 uint8_t spi_readmode_f15_mod_60_6f; 172 uint8_t fast_speed_new_f15_mod_60_6f; 173 uint8_t reserved_42h; 174 uint8_t spi_readmode_f17_mod_00_2f; 175 uint8_t spi_fastspeed_f17_mod_00_2f; 176 uint8_t qpr_dummy_cycle_f17_mod_00_2f; 177 uint8_t reserved_46h; 178 uint8_t spi_readmode_f17_mod_30_3f; 179 uint8_t spi_fastspeed_f17_mod_30_3f; 180 uint8_t micron_detect_f17_mod_30_3f; 181 uint8_t reserved_4Ah; 182 uint8_t reserved_4Bh; 183 uint32_t reserved_4Ch; 184 } __attribute__((packed, aligned(16))) embedded_firmware; 185 186 typedef struct _psp_directory_header { 187 uint32_t cookie; 188 uint32_t checksum; 189 uint32_t num_entries; 190 union { 191 uint32_t additional_info; 192 struct { 193 uint32_t dir_size:10; 194 uint32_t spi_block_size:4; 195 uint32_t base_addr:15; 196 uint32_t address_mode:2; 197 uint32_t not_used:1; 198 } __attribute__((packed)) additional_info_fields; 199 }; 200 } __attribute__((packed, aligned(16))) psp_directory_header; 201 202 typedef struct _psp_directory_entry { 203 uint8_t type; 204 uint8_t subprog; 205 union { 206 uint16_t rsvd; 207 struct { 208 uint8_t rom_id:2; 209 uint8_t writable:1; 210 uint8_t inst:4; 211 uint8_t rsvd_1:1; 212 uint8_t rsvd_2:8; 213 } __attribute__((packed)); 214 }; 215 uint32_t size; 216 uint64_t addr:62; /* or a value in some cases */ 217 uint64_t address_mode:2; 218 } __attribute__((packed)) psp_directory_entry; 219 220 typedef struct _psp_directory_table { 221 psp_directory_header header; 222 psp_directory_entry entries[]; 223 } __attribute__((packed, aligned(16))) psp_directory_table; 224 225 #define MAX_PSP_ENTRIES 0xff 226 227 typedef struct _psp_combo_header { 228 uint32_t cookie; 229 uint32_t checksum; 230 uint32_t num_entries; 231 uint32_t lookup; 232 uint64_t reserved[2]; 233 } __attribute__((packed, aligned(16))) psp_combo_header; 234 235 typedef struct _psp_combo_entry { 236 uint32_t id_sel; 237 uint32_t id; 238 uint64_t lvl2_addr; 239 } __attribute__((packed)) psp_combo_entry; 240 241 typedef struct _psp_combo_directory { 242 psp_combo_header header; 243 psp_combo_entry entries[]; 244 } __attribute__((packed, aligned(16))) psp_combo_directory; 245 246 #define MAX_COMBO_ENTRIES 2 247 248 typedef struct _bios_directory_hdr { 249 uint32_t cookie; 250 uint32_t checksum; 251 uint32_t num_entries; 252 union { 253 uint32_t additional_info; 254 struct { 255 uint32_t dir_size:10; 256 uint32_t spi_block_size:4; 257 uint32_t base_addr:15; 258 uint32_t address_mode:2; 259 uint32_t not_used:1; 260 } __attribute__((packed)) additional_info_fields; 261 }; 262 } __attribute__((packed, aligned(16))) bios_directory_hdr; 263 264 typedef struct _bios_directory_entry { 265 uint8_t type; 266 uint8_t region_type; 267 int reset:1; 268 int copy:1; 269 int ro:1; 270 int compressed:1; 271 int inst:4; 272 uint8_t subprog; /* b[7:3] reserved */ 273 uint32_t size; 274 uint64_t source:62; 275 uint64_t address_mode:2; 276 uint64_t dest; 277 } __attribute__((packed)) bios_directory_entry; 278 279 typedef struct _bios_directory_table { 280 bios_directory_hdr header; 281 bios_directory_entry entries[]; 282 } bios_directory_table; 283 284 #define MAX_BIOS_ENTRIES 0x2f 285 286 #define BDT_LVL1 (1 << 0) 287 #define BDT_LVL2 (1 << 1) 288 #define BDT_LVL1_AB (1 << 2) 289 #define BDT_LVL2_AB (1 << 3) 290 #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) 291 #define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB) 292 typedef struct _amd_bios_entry { 293 amd_bios_type type; 294 char *filename; 295 int subpr; 296 int region_type; 297 int reset; 298 int copy; 299 int ro; 300 int zlib; 301 int inst; 302 uint64_t src; 303 uint64_t dest; 304 size_t size; 305 int level; 306 } amd_bios_entry; 307 308 typedef struct _ish_directory_table { 309 uint32_t checksum; 310 uint32_t boot_priority; 311 uint32_t update_retry_count; 312 uint8_t glitch_retry_count; 313 uint8_t glitch_higherbits_reserved[3]; 314 uint32_t pl2_location; 315 uint32_t psp_id; 316 uint32_t slot_max_size; 317 uint32_t reserved; 318 } __attribute__((packed)) ish_directory_table; 319 320 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa 321 #define PSP_COOKIE 0x50535024 /* 'PSP$' */ 322 #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ 323 #define PSP2_COOKIE 0x50535032 /* 'PSP2' */ 324 #define BHD_COOKIE 0x44484224 /* 'DHB$ */ 325 #define BHDL2_COOKIE 0x324c4224 /* '2LB$ */ 326 #define BHD2_COOKIE 0x44484232 /* 'DHB2' */ 327 328 #define PSP_LVL1 (1 << 0) 329 #define PSP_LVL2 (1 << 1) 330 #define PSP_LVL1_AB (1 << 2) 331 #define PSP_LVL2_AB (1 << 3) 332 #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) 333 #define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) 334 335 typedef enum _fwid_type { 336 FWID_TYPE_FWID = 0, 337 FWID_TYPE_UUID, 338 } fwid_type_t; 339 340 #define UUID_LEN_BYTES 16 341 typedef struct _amd_fw_entry_hash { 342 fwid_type_t fwid_type; 343 union { 344 uint16_t fw_id; 345 uint8_t uuid[UUID_LEN_BYTES]; 346 }; 347 uint16_t subtype; 348 uint32_t sha_len; 349 uint8_t sha[SHA384_DIGEST_LENGTH]; 350 } amd_fw_entry_hash; 351 352 typedef struct _amd_fw_entry { 353 amd_fw_type type; 354 char *filename; 355 uint8_t subprog; 356 uint8_t inst; 357 uint64_t dest; 358 size_t size; 359 int level; 360 uint64_t other; 361 /* If the binary is signed and the tool is invoked to keep the signed binaries separate, 362 then this field is populated with the offset of the concerned PSP binary (relative to 363 BIOS or PSP Directory table). */ 364 uint64_t addr_signed; 365 uint32_t file_size; 366 /* Some files that don't have amd_fw_header have to be skipped from hashing. These files 367 include but not limited to: *iKek*, *.tkn, *.stkn */ 368 bool skip_hashing; 369 uint8_t hash_tbl_id; 370 fwid_type_t fwid_type; 371 uint32_t num_hash_entries; 372 amd_fw_entry_hash *hash_entries; 373 bool generate_manifest; 374 } amd_fw_entry; 375 376 /* Most PSP binaries, if not all, have the following header format. */ 377 struct amd_fw_header { 378 uint8_t reserved_0[20]; 379 uint32_t fw_size_signed; 380 uint8_t reserved_18[24]; 381 /* 1 if the image is signed, 0 otherwise */ 382 uint32_t sig_opt; 383 uint32_t sig_id; 384 uint8_t sig_param[16]; 385 uint32_t comp_opt; 386 uint8_t reserved_4c[4]; 387 uint32_t uncomp_size; 388 uint32_t comp_size; 389 /* Starting MDN fw_id is populated instead of fw_type. */ 390 uint16_t fw_id; 391 uint8_t reserved_5a[6]; 392 uint8_t version[4]; 393 uint8_t reserved_64[8]; 394 uint32_t size_total; 395 uint8_t reserved_70[12]; 396 /* Starting MDN fw_id is populated instead of fw_type. fw_type will still be around 397 for backwards compatibility. */ 398 uint8_t fw_type; 399 uint8_t fw_subtype; 400 uint8_t fw_subprog; 401 uint8_t reserved_7f; 402 uint8_t reserved_80[128]; 403 } __packed; 404 405 /* Based on the available PSP resources and increasing number of signed PSP binaries, 406 AMD recommends to split the hash table into 3 parts for now. */ 407 #define MAX_NUM_HASH_TABLES 3 408 struct psp_fw_hash_table { 409 uint16_t version; 410 uint16_t no_of_entries_256; 411 uint16_t no_of_entries_384; 412 /* The next 2 elements are pointers to arrays of SHA256 and SHA384 entries. */ 413 /* It does not make sense to store pointers in the CBFS file */ 414 } __packed; 415 416 typedef struct _amd_cb_config { 417 bool have_whitelist; 418 bool unlock_secure; 419 bool use_secureos; 420 bool load_mp2_fw; 421 bool multi_level; 422 bool s0i3; 423 bool second_gen; 424 bool have_mb_spl; 425 bool recovery_ab; 426 bool recovery_ab_single_copy; 427 bool need_ish; 428 bool use_combo; 429 bool combo_new_rab; /* new combo layout for recovery A/B */ 430 bool have_apcb_bk; 431 enum platform soc_id; 432 433 uint8_t efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag; 434 uint32_t body_location, efs_location; 435 uint64_t signed_start_addr; 436 char *manifest_file; 437 const char *signed_output_file; 438 char *output, *config; 439 char *combo_config[MAX_COMBO_ENTRIES]; 440 int debug; 441 } amd_cb_config; 442 443 typedef struct _context { 444 char *rom; /* target buffer, size of flash device */ 445 uint32_t rom_size; /* size of flash device */ 446 uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ 447 uint32_t current; /* pointer within flash & proxy buffer */ 448 uint32_t current_pointer_saved; 449 uint32_t current_table; 450 void *amd_psp_fw_table_clean; 451 void *amd_bios_table_clean; 452 struct _combo_apcb { 453 char *filename; 454 uint8_t ins; 455 uint8_t sub; 456 } combo_apcb[MAX_COMBO_ENTRIES], combo_apcb_bk[MAX_COMBO_ENTRIES]; 457 embedded_firmware *amd_romsig_ptr; 458 psp_directory_table *pspdir, *pspdir_bak, *pspdir2, *pspdir2_b; 459 bios_directory_table *biosdir, *biosdir2, *biosdir2_b; 460 psp_combo_directory *psp_combo_dir, *bhd_combo_dir; 461 ish_directory_table *ish_a_dir, *ish_b_dir; 462 } context; 463 464 uint8_t process_config(FILE *config, amd_cb_config *cb_config); 465 void process_signed_psp_firmwares(const char *signed_rom, 466 amd_fw_entry *fw_table, 467 uint64_t signed_start_addr, 468 enum platform soc_id); 469 int find_bios_entry(amd_bios_type type); 470 bool needs_ish(enum platform platform_type); 471 472 #define EFS_FILE_SUFFIX ".efs" 473 #define TMP_FILE_SUFFIX ".tmp" 474 #define BODY_FILE_SUFFIX ".body" 475 476 void write_or_fail(int fd, void *ptr, size_t size); 477 ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size); 478 ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size); 479 ssize_t write_body(char *output, void *body_offset, ssize_t body_size); 480 ssize_t copy_blob(void *dest, const char *src_file, size_t room); 481 #define OK 0 482 483 #define LINE_EOF (1) 484 #define LINE_TOO_LONG (2) 485 486 int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx); 487 void register_apcb_combo(amd_cb_config *cb_config, int combo_index, context *ctx); 488 489 #endif /* _AMD_FW_TOOL_H_ */