bd82x6x.go
1 package main 2 3 import "fmt" 4 5 type bd82x6x struct { 6 variant string 7 node *DevTreeNode 8 } 9 10 func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { 11 portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] 12 if !ok { 13 return false 14 } 15 return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 16 } 17 18 func ich9GetFlashSize(ctx Context) { 19 inteltool := ctx.InfoSource.GetInteltool() 20 switch (inteltool.RCBA[0x3410] >> 10) & 3 { 21 /* SPI. All boards I've seen with sandy/ivy use SPI. */ 22 case 3: 23 ROMProtocol = "SPI" 24 highflkb := uint32(0) 25 for reg := uint16(0); reg < 5; reg++ { 26 fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff 27 flkb := (fl + 1) << 2 28 if flkb > highflkb { 29 highflkb = flkb 30 } 31 } 32 ROMSizeKB = int(highflkb) 33 /* Shared with ME. Flashrom is unable to handle it. */ 34 FlashROMSupport = "n" 35 } 36 } 37 38 func (b bd82x6x) GetGPIOHeader() string { 39 return "southbridge/intel/bd82x6x/pch.h" 40 } 41 42 func (b bd82x6x) EnableGPE(in int) { 43 b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" 44 } 45 46 func (b bd82x6x) EncodeGPE(in int) int { 47 return in + 0x10 48 } 49 50 func (b bd82x6x) DecodeGPE(in int) int { 51 return in - 0x10 52 } 53 54 func (b bd82x6x) NeedRouteGPIOManually() { 55 b.node.Comment += ", FIXME: set gpiX_routing for EC support" 56 } 57 58 func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { 59 60 SouthBridge = &b 61 62 inteltool := ctx.InfoSource.GetInteltool() 63 GPIO(ctx, inteltool) 64 65 KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true 66 KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true 67 KconfigInt["USBDEBUG_HCD_INDEX"] = 2 68 KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" 69 dmi := ctx.InfoSource.GetDMI() 70 if dmi.Vendor == "LENOVO" { 71 KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 72 } else { 73 KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 74 } 75 KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" 76 77 ich9GetFlashSize(ctx) 78 79 DSDTDefines = append(DSDTDefines, 80 DSDTDefine{ 81 Key: "BRIGHTNESS_UP", 82 Value: "\\_SB.PCI0.GFX0.INCB", 83 }, 84 DSDTDefine{ 85 Key: "BRIGHTNESS_DOWN", 86 Value: "\\_SB.PCI0.GFX0.DECB", 87 }) 88 89 FADT := ctx.InfoSource.GetACPI()["FACP"] 90 91 pcieHotplugMap := "{ " 92 93 for port := 0; port < 7; port++ { 94 if b.IsPCIeHotplug(ctx, port) { 95 pcieHotplugMap += "1, " 96 } else { 97 pcieHotplugMap += "0, " 98 } 99 } 100 101 if b.IsPCIeHotplug(ctx, 7) { 102 pcieHotplugMap += "1 }" 103 } else { 104 pcieHotplugMap += "0 }" 105 } 106 107 pchComment := "Intel Series " 108 if b.variant == "BD82X6X" { 109 pchComment += "6 Cougar Point PCH" 110 } else { 111 pchComment += "7 Panther Point PCH" 112 } 113 114 cur := DevTreeNode{ 115 Chip: "southbridge/intel/bd82x6x", 116 Comment: pchComment, 117 118 Registers: map[string]string{ 119 "sata_interface_speed_support": "0x3", 120 "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), 121 "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), 122 "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), 123 "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), 124 "pcie_port_coalesce": "1", 125 "pcie_hotplug_map": pcieHotplugMap, 126 127 "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), 128 129 "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), 130 "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), 131 "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), 132 }, 133 PCISlots: []PCISlot{ 134 PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci"}, 135 PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1"}, 136 PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2"}, 137 PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r"}, 138 PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt"}, 139 PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe"}, 140 PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2"}, 141 PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda"}, 142 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1"}, 143 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2"}, 144 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3"}, 145 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4"}, 146 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5"}, 147 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6"}, 148 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7"}, 149 PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8"}, 150 PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1"}, 151 PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge"}, 152 PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc"}, 153 PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1"}, 154 PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus"}, 155 PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2"}, 156 PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal"}, 157 }, 158 } 159 160 b.node = &cur 161 162 xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}] 163 164 if ok { 165 cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8]) 166 cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0]) 167 cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) 168 } 169 170 PutPCIChip(addr, cur) 171 PutPCIDevParent(addr, "", "lpc") 172 173 DSDTIncludes = append(DSDTIncludes, DSDTInclude{ 174 File: "southbridge/intel/common/acpi/platform.asl", 175 }) 176 DSDTIncludes = append(DSDTIncludes, DSDTInclude{ 177 File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", 178 }) 179 DSDTIncludes = append(DSDTIncludes, DSDTInclude{ 180 File: "southbridge/intel/common/acpi/sleepstates.asl", 181 }) 182 DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ 183 File: "southbridge/intel/bd82x6x/acpi/pch.asl", 184 }) 185 186 AddBootBlockFile("early_init.c", "") 187 AddROMStageFile("early_init.c", "") 188 189 sb := Create(ctx, "early_init.c") 190 defer sb.Close() 191 Add_SPDX(sb, C, GPL2_only) 192 193 sb.WriteString(`#include <bootblock_common.h> 194 #include <device/pci_ops.h> 195 #include <southbridge/intel/bd82x6x/pch.h> 196 `) 197 usbPortConfig := "{\n" 198 199 currentMap := map[uint32]int{ 200 0x20000153: 0, 201 0x20000f57: 1, 202 0x2000055b: 2, 203 0x20000f51: 3, 204 0x2000094a: 4, 205 0x2000035f: 5, 206 0x20000f53: 6, 207 0x20000f5b: 7, 208 0x20000553: 9, 209 } 210 211 for port := uint(0); port < 14; port++ { 212 var pinmask uint32 213 OCPin := -1 214 if port < 8 { 215 pinmask = inteltool.RCBA[0x35a0] 216 } else { 217 pinmask = inteltool.RCBA[0x35a4] 218 } 219 for pin := uint(0); pin < 4; pin++ { 220 if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { 221 OCPin = int(pin) 222 if port >= 8 { 223 OCPin += 4 224 } 225 } 226 } 227 current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] 228 if !ok { 229 usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, 0x%x, %d},\n", 230 ((inteltool.RCBA[0x359c]>>port)&1)^1, 231 inteltool.RCBA[uint16(0x3500+4*port)] & 0xfff, 232 OCPin) 233 } else { 234 usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, %d, %d},\n", 235 ((inteltool.RCBA[0x359c]>>port)&1)^1, 236 current, 237 OCPin) 238 } 239 } 240 usbPortConfig += "\t\t\t}" 241 cur.Registers["usb_port_config"] = usbPortConfig 242 243 sb.WriteString(` 244 void bootblock_mainboard_early_init(void) 245 { 246 `) 247 RestorePCI16Simple(sb, addr, 0x82) 248 249 RestorePCI16Simple(sb, addr, 0x80) 250 251 sb.WriteString("}\n") 252 253 gnvs := Create(ctx, "acpi_tables.c") 254 defer gnvs.Close() 255 256 Add_SPDX(gnvs, C, GPL2_only) 257 gnvs.WriteString(`#include <acpi/acpi_gnvs.h> 258 #include <soc/nvs.h> 259 260 /* FIXME: check this function. */ 261 void mainboard_fill_gnvs(struct global_nvs *gnvs) 262 { 263 /* The lid is open by default. */ 264 gnvs->lids = 1; 265 266 /* Temperature at which OS will shutdown */ 267 gnvs->tcrt = 100; 268 /* Temperature at which OS will throttle CPU */ 269 gnvs->tpsv = 90; 270 } 271 `) 272 } 273 274 func init() { 275 /* BD82X6X LPC */ 276 for id := 0x1c40; id <= 0x1c5f; id++ { 277 RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"}) 278 } 279 280 /* C216 LPC */ 281 for id := 0x1e41; id <= 0x1e5f; id++ { 282 RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"}) 283 } 284 285 /* PCIe bridge */ 286 for _, id := range []uint16{ 287 0x1c10, 0x1c12, 0x1c14, 0x1c16, 288 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, 289 0x1e10, 0x1e12, 0x1e14, 0x1e16, 290 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, 291 0x1e25, 0x244e, 0x2448, 292 } { 293 RegisterPCI(0x8086, id, GenericPCI{}) 294 } 295 296 /* SMBus controller */ 297 RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) 298 RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) 299 300 /* SATA */ 301 for _, id := range []uint16{ 302 0x1c00, 0x1c01, 0x1c02, 0x1c03, 303 0x1e00, 0x1e01, 0x1e02, 0x1e03, 304 } { 305 RegisterPCI(0x8086, id, GenericPCI{}) 306 } 307 308 /* EHCI */ 309 for _, id := range []uint16{ 310 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, 311 } { 312 RegisterPCI(0x8086, id, GenericPCI{}) 313 } 314 315 /* XHCI */ 316 RegisterPCI(0x8086, 0x1e31, GenericPCI{}) 317 318 /* ME and children */ 319 for _, id := range []uint16{ 320 0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d, 321 0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d, 322 } { 323 RegisterPCI(0x8086, id, GenericPCI{}) 324 } 325 326 /* Ethernet */ 327 RegisterPCI(0x8086, 0x1502, GenericPCI{}) 328 RegisterPCI(0x8086, 0x1503, GenericPCI{}) 329 330 }