1  # This program is free software: you can redistribute it and/or modify
  2  # it under the terms of the GNU General Public License as published by
  3  # the Free Software Foundation, either version 3 of the License, or
  4  # (at your option) any later version.
  5  #
  6  # This program is distributed in the hope that it will be useful,
  7  # but WITHOUT ANY WARRANTY; without even the implied warranty of
  8  # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  9  # GNU General Public License for more details.
 10  
 11  #
 12  # Info on flash descriptor (page 845 onwards):
 13  #
 14  # http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf
 15  
 16  # Flash Descriptor SPEC for GM45/ICH9M
 17  {
 18  	# Signature for descriptor mode
 19  	"fd_signature"		: 32,
 20  
 21  	# Flash map registers
 22  	"flmap0_fcba"		: 8,
 23  	"flmap0_nc"		: 2,
 24  	"flmap0_reserved0"	: 6,
 25  	"flmap0_frba"		: 8,
 26  	"flmap0_nr"		: 3,
 27  	"flmap0_reserved1"	: 5,
 28  	"flmap1_fmba"		: 8,
 29  	"flmap1_nm"		: 3,
 30  	"flmap1_reserved"	: 5,
 31  	"flmap1_fisba"		: 8,
 32  	"flmap1_isl"		: 8,
 33  	"flmap2_fmsba"		: 8,
 34  	"flmap2_msl"		: 8,
 35  	"flmap2_reserved"	: 16,
 36  
 37  	# Component section
 38  	"flcomp_density1"	: 3,
 39  	"flcomp_density2"	: 3,
 40  	"flcomp_reserved0"	: 2,
 41  	"flcomp_reserved1"	: 8,
 42  	"flcomp_reserved2"	: 1,
 43  	"flcomp_readclockfreq"	: 3,
 44  	"flcomp_fastreadsupp"	: 1,
 45  	"flcomp_fastreadfreq"	: 3,
 46  	"flcomp_w_eraseclkfreq"	: 3,
 47  	"flcomp_r_statclkfreq"	: 3,
 48  	"flcomp_reserved3"	: 2,
 49  	"flill"			: 32,
 50  	"flbp"			: 32,
 51  	"comp_padding"[36]	: 8,
 52  
 53  	# Region section
 54  	"flreg0_base"		: 13,
 55  	"flreg0_reserved0"	: 3,
 56  	"flreg0_limit"		: 13,
 57  	"flreg0_reserved1"	: 3,
 58  	"flreg1_base"		: 13,
 59  	"flreg1_reserved0"	: 3,
 60  	"flreg1_limit"		: 13,
 61  	"flreg1_reserved1"	: 3,
 62  	"flreg2_base"		: 13,
 63  	"flreg2_reserved0"	: 3,
 64  	"flreg2_limit"		: 13,
 65  	"flreg2_reserved1"	: 3,
 66  	"flreg3_base"		: 13,
 67  	"flreg3_reserved0"	: 3,
 68  	"flreg3_limit"		: 13,
 69  	"flreg3_reserved1"	: 3,
 70  	"flreg4_base"		: 13,
 71  	"flreg4_reserved0"	: 3,
 72  	"flreg4_limit"		: 13,
 73  	"flreg4_reserved1"	: 3,
 74  	"flreg_padding"[12]	: 8,
 75  
 76  	# Master access section
 77  
 78  	# 1: Host CPU/BIOS
 79  	"flmstr1_requesterid"	: 16,
 80  	"flmstr1_r_fd"		: 1,
 81  	"flmstr1_r_bios"	: 1,
 82  	"flmstr1_r_me"		: 1,
 83  	"flmstr1_r_gbe"		: 1,
 84  	"flmstr1_r_pd"		: 1,
 85  	"flmstr1_r_reserved"	: 3,
 86  	"flmstr1_w_fd"		: 1,
 87  	"flmstr1_w_bios"	: 1,
 88  	"flmstr1_w_me"		: 1,
 89  	"flmstr1_w_gbe"		: 1,
 90  	"flmstr1_w_pd"		: 1,
 91  	"flmstr1_w_reserved"	: 3,
 92  
 93  	# 2: ME
 94  	"flmstr2_requesterid"	: 16,
 95  	"flmstr2_r_fd"		: 1,
 96  	"flmstr2_r_bios"	: 1,
 97  	"flmstr2_r_me"		: 1,
 98  	"flmstr2_r_gbe"		: 1,
 99  	"flmstr2_r_pd"		: 1,
100  	"flmstr2_r_reserved"	: 3,
101  	"flmstr2_w_fd"		: 1,
102  	"flmstr2_w_bios"	: 1,
103  	"flmstr2_w_me"		: 1,
104  	"flmstr2_w_gbe"		: 1,
105  	"flmstr2_w_pd"		: 1,
106  	"flmstr2_w_reserved"	: 3,
107  
108  	# 3: GbE
109  	"flmstr3_requesterid"	: 16,
110  	"flmstr3_r_fd"		: 1,
111  	"flmstr3_r_bios"	: 1,
112  	"flmstr3_r_me"		: 1,
113  	"flmstr3_r_gbe"		: 1,
114  	"flmstr3_r_pd"		: 1,
115  	"flmstr3_r_reserved"	: 3,
116  	"flmstr3_w_fd"		: 1,
117  	"flmstr3_w_bios"	: 1,
118  	"flmstr3_w_me"		: 1,
119  	"flmstr3_w_gbe"		: 1,
120  	"flmstr3_w_pd"		: 1,
121  	"flmstr3_w_reserved"	: 3,
122  
123  	"flmstr_padding"[148]	: 8,
124  
125  	# ICHSTRAP0
126  	"ich0_medisable"	: 1,
127  	"ich0_reserved0"	: 6,
128  	"ich0_tcomode"		: 1,
129  	"ich0_mesmbusaddr"	: 7,
130  	"ich0_bmcmode"		: 1,
131  	"ich0_trippointsel"	: 1,
132  	"ich0_reserved1"	: 2,
133  	"ich0_integratedgbe"	: 1,
134  	"ich0_lanphy"		: 1,
135  	"ich0_reserved2"	: 3,
136  	"ich0_dmireqiddisable"	: 1,
137  	"ich0_me2smbusaddr"	: 7,
138  
139  	# ICHSTRAP1
140  	"ich1_dynclk_nmlink"	: 1,
141  	"ich1_dynclk_smlink"	: 1,
142  	"ich1_dynclk_mesmbus"	: 1,
143  	"ich1_dynclk_sst"	: 1,
144  	"ich1_reserved0"	: 4,
145  	"ich1_nmlink_npostreqs"	: 1,
146  	"ich1_reserved1"	: 7,
147  	"ich1_reserved2"	: 16,
148  
149  	"ichstrap_padding"[248]	: 8,
150  
151  	# MCHSTRAP0
152  	"mch0_medisable"	: 1,
153  	"mch0_mebootfromflash"	: 1,
154  	"mch0_tpmdisable"	: 1,
155  	"mch0_reserved0"	: 3,
156  	"mch0_spifingerprinton"	: 1,
157  	# Alternate disable - allows ME to perform chipset
158  	# init functions but disables FW apps such as AMT
159  	"mch0_mealtdisable"	: 1,
160  	"mch0_reserved1"	: 8,
161  	"mch0_reserved2"	: 16,
162  
163  	"mchstrap_padding"[3292]: 8,
164  
165  	# ME VSCC Table
166  	"mevscc_jid0"		: 32,
167  	"mevscc_vscc0"		: 32,
168  	"mevscc_jid1"		: 32,
169  	"mevscc_vscc1"		: 32,
170  	"mevscc_jid2"		: 32,
171  	"mevscc_vscc2"		: 32,
172  	"mevscc_padding"[4]	: 8,
173  
174  	# Descriptor Map 2 Record
175  	"mevscc_tablebase"	: 8,
176  	"mevscc_tablelength"	: 8,
177  	"mevscc_reserved"	: 16,
178  
179  	# OEM section
180  	"oem_magic"[8]		: 8,
181  	"oem_padding"[248]	: 8
182  }