1  /* ifdtool - dump Intel Firmware Descriptor information */
  2  /* SPDX-License-Identifier: GPL-2.0-only */
  3  
  4  #include <stdint.h>
  5  #include <stdbool.h>
  6  #define IFDTOOL_VERSION "1.2"
  7  
  8  enum ifd_version {
  9  	IFD_VERSION_1,
 10  	IFD_VERSION_1_5,
 11  	IFD_VERSION_2,
 12  };
 13  
 14  /* port from flashrom */
 15  enum ich_chipset {
 16  	CHIPSET_ICH_UNKNOWN,
 17  	CHIPSET_ICH8,
 18  	CHIPSET_ICH9,
 19  	CHIPSET_ICH10,
 20  	CHIPSET_PCH_UNKNOWN,
 21  	CHIPSET_5_SERIES_IBEX_PEAK,
 22  	CHIPSET_6_SERIES_COUGAR_POINT,
 23  	CHIPSET_7_SERIES_PANTHER_POINT,
 24  	CHIPSET_8_SERIES_LYNX_POINT,
 25  	CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
 26  			   * Bay Trail, Avoton/Rangeley
 27  			   */
 28  	CHIPSET_8_SERIES_LYNX_POINT_LP,
 29  	CHIPSET_8_SERIES_WELLSBURG,
 30  	CHIPSET_9_SERIES_WILDCAT_POINT,
 31  	CHIPSET_9_SERIES_WILDCAT_POINT_LP,
 32  	CHIPSET_N_J_SERIES_APOLLO_LAKE, /* Apollo Lake: N3xxx, J3xxx */
 33  	CHIPSET_N_J_SERIES_GEMINI_LAKE, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
 34  	CHIPSET_N_SERIES_JASPER_LAKE, /* Jasper Lake: N6xxx, N51xx, N45xx */
 35  	CHIPSET_x6000_SERIES_ELKHART_LAKE, /* Elkhart Lake: x6000 */
 36  	CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
 37  	CHIPSET_300_SERIES_CANNON_POINT, /* 8th-9th gen Core i/o (LP) variants */
 38  	CHIPSET_400_SERIES_ICE_POINT, /* 10th gen Core i/o (LP) variants */
 39  	CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
 40  						   * variants onwards */
 41  	CHIPSET_800_SERIES_METEOR_LAKE, /* 14th gen Core i/o (LP) variants onwards */
 42  	CHIPSET_900_SERIES_PANTHER_LAKE, /* 16th gen Core i/o (LP) variants onwards */
 43  	CHIPSET_C620_SERIES_LEWISBURG,
 44  	CHIPSET_DENVERTON,
 45  };
 46  
 47  enum platform {
 48  	PLATFORM_APL,
 49  	PLATFORM_CNL,
 50  	PLATFORM_LBG,
 51  	PLATFORM_EHL,
 52  	PLATFORM_GLK,
 53  	PLATFORM_ICL,
 54  	PLATFORM_JSL,
 55  	PLATFORM_SKLKBL,
 56  	PLATFORM_TGL,
 57  	PLATFORM_ADL,
 58  	PLATFORM_IFD2,
 59  	PLATFORM_DNV,
 60  	PLATFORM_MTL,
 61  	PLATFORM_PTL,
 62  	PLATFORM_WBG
 63  };
 64  
 65  #define LAYOUT_LINELEN 80
 66  
 67  enum spi_frequency {
 68  	SPI_FREQUENCY_20MHZ = 0,
 69  	SPI_FREQUENCY_33MHZ = 1,
 70  	SPI_FREQUENCY_48MHZ = 2,
 71  	SPI_FREQUENCY_50MHZ_30MHZ = 4,
 72  	SPI_FREQUENCY_17MHZ = 6,
 73  };
 74  
 75  enum spi_frequency_500_series {
 76  	SPI_FREQUENCY_100MHZ = 0,
 77  	SPI_FREQUENCY_50MHZ = 1,
 78  	SPI_FREQUENCY_500SERIES_33MHZ = 3,
 79  	SPI_FREQUENCY_25MHZ = 4,
 80  	SPI_FREQUENCY_14MHZ = 6,
 81  };
 82  
 83  enum espi_frequency {
 84  	ESPI_FREQUENCY_20MHZ = 0,
 85  	ESPI_FREQUENCY_24MHZ = 1,
 86  	ESPI_FREQUENCY_30MHZ = 2,
 87  	ESPI_FREQUENCY_48MHZ = 3,
 88  	ESPI_FREQUENCY_60MHZ = 4,
 89  	ESPI_FREQUENCY_17MHZ = 6,
 90  };
 91  
 92  enum espi_frequency_500_series {
 93  	ESPI_FREQUENCY_500SERIES_20MHZ = 0,
 94  	ESPI_FREQUENCY_500SERIES_24MHZ = 1,
 95  	ESPI_FREQUENCY_500SERIES_25MHZ = 2,
 96  	ESPI_FREQUENCY_500SERIES_48MHZ = 3,
 97  	ESPI_FREQUENCY_500SERIES_60MHZ = 4,
 98  };
 99  
100  enum espi_frequency_800_series {
101  	ESPI_FREQUENCY_800SERIES_20MHZ = 0,
102  	ESPI_FREQUENCY_800SERIES_25MHZ = 1,
103  	ESPI_FREQUENCY_800SERIES_33MHZ = 2,
104  	ESPI_FREQUENCY_800SERIES_50MHZ = 4,
105  };
106  
107  enum component_density {
108  	COMPONENT_DENSITY_512KB = 0,
109  	COMPONENT_DENSITY_1MB   = 1,
110  	COMPONENT_DENSITY_2MB   = 2,
111  	COMPONENT_DENSITY_4MB   = 3,
112  	COMPONENT_DENSITY_8MB   = 4,
113  	COMPONENT_DENSITY_16MB  = 5,
114  	COMPONENT_DENSITY_32MB  = 6,
115  	COMPONENT_DENSITY_64MB  = 7,
116  	COMPONENT_DENSITY_UNUSED = 0xf
117  };
118  
119  // flash descriptor
120  struct __packed fdbar {
121  	uint32_t flvalsig;
122  	uint32_t flmap0;
123  	uint32_t flmap1;
124  	uint32_t flmap2;
125  	uint32_t flmap3; // Exist for 500 series onwards
126  };
127  
128  // regions
129  #define MAX_REGIONS 16
130  #define MAX_REGIONS_OLD 5
131  
132  enum flash_regions {
133  	REGION_DESC,
134  	REGION_BIOS,
135  	REGION_ME,
136  	REGION_GBE,
137  	REGION_PDR,
138  	REGION_DEV_EXP1,
139  	REGION_BIOS2,
140  	REGION_EC = 8,
141  	REGION_DEV_EXP2,
142  	REGION_IE,
143  	REGION_10GB_0,
144  	REGION_10GB_1,
145  	REGION_PTT = 15,
146  };
147  
148  struct __packed frba {
149  	uint32_t flreg[MAX_REGIONS];
150  };
151  
152  // component section
153  struct __packed fcba {
154  	uint32_t flcomp;
155  	uint32_t flill;
156  	uint32_t flpb;
157  };
158  
159  // pch strap
160  #define MAX_PCHSTRP 1024
161  
162  struct __packed fpsba {
163  	uint32_t pchstrp[MAX_PCHSTRP];
164  };
165  
166  /*
167   * WR / RD bits start at different locations within the flmstr regs, but
168   * otherwise have identical meaning.
169   */
170  #define FLMSTR_WR_SHIFT_V1 24
171  #define FLMSTR_WR_SHIFT_V2 20
172  #define FLMSTR_RD_SHIFT_V1 16
173  #define FLMSTR_RD_SHIFT_V2 8
174  
175  // master
176  struct __packed fmba {
177  	uint32_t flmstr1;
178  	uint32_t flmstr2;
179  	uint32_t flmstr3;
180  	uint32_t flmstr4;
181  	uint32_t flmstr5;
182  	uint32_t flmstr6;
183  };
184  
185  // processor strap
186  struct __packed fmsba {
187  	uint32_t data[8];
188  };
189  
190  // ME VSCC
191  struct vscc {
192  	uint32_t jid;
193  	uint32_t vscc;
194  };
195  
196  struct vtba {
197  	// Actual number of entries specified in vtl
198  	/* FIXME: Rationale for the limit of 8.
199  	 *        AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
200  	struct vscc entry[8];
201  };
202  
203  struct region {
204  	int base, limit, size, type;
205  };
206  
207  struct region_name {
208  	const char *pretty;
209  	const char *terse;
210  	const char *filename;
211  	const char *fmapname;
212  };
213  
214  struct cse_fpt {
215  	const char signature[4];
216  	uint32_t count;
217  	uint8_t header_version;
218  	uint8_t entry_version;
219  	uint8_t length;
220  	uint8_t crc;
221  	uint8_t reserved[20];
222  };
223  
224  struct cse_fpt_sub_part {
225  	const char signature[4];
226  	uint32_t reserved_1;
227  	uint32_t offset;
228  	uint32_t length;
229  	uint8_t reserved_2[12];
230  	uint32_t flags;
231  };