geodegx2.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include "msrtool.h" 4 5 int geodegx2_probe(const struct targetdef *target, const struct cpuid_t *id) { 6 return 5 == id->family && 5 == id->model; 7 } 8 9 const struct msrdef geodegx2_msrs[] = { 10 { 0x10000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM0", "GLIU0 P2D Base Mask Descriptor 0", { 11 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 12 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 13 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 14 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 15 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 16 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 17 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 18 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 19 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 20 { BITVAL_EOT } 21 }}, 22 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 23 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 24 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 25 { BITVAL_EOT } 26 }}, 27 { 59, 20, RESERVED }, 28 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 29 { BITVAL_EOT } 30 }}, 31 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 32 { BITVAL_EOT } 33 }}, 34 { BITS_EOT } 35 }}, 36 { 0x10000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM1", "GLIU0 P2D Base Mask Descriptor 1", { 37 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 38 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 39 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 40 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 41 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 42 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 43 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 44 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 45 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 46 { BITVAL_EOT } 47 }}, 48 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 49 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 50 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 51 { BITVAL_EOT } 52 }}, 53 { 59, 20, RESERVED }, 54 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 55 { BITVAL_EOT } 56 }}, 57 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 58 { BITVAL_EOT } 59 }}, 60 { BITS_EOT } 61 }}, 62 { 0x10000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM2", "GLIU0 P2D Base Mask Descriptor 2", { 63 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 64 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 65 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 66 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 67 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 68 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 69 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 70 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 71 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 72 { BITVAL_EOT } 73 }}, 74 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 75 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 76 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 77 { BITVAL_EOT } 78 }}, 79 { 59, 20, RESERVED }, 80 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 81 { BITVAL_EOT } 82 }}, 83 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 84 { BITVAL_EOT } 85 }}, 86 { BITS_EOT } 87 }}, 88 { 0x10000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM3", "GLIU0 P2D Base Mask Descriptor 3", { 89 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 90 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 91 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 92 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 93 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 94 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 95 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 96 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 97 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 98 { BITVAL_EOT } 99 }}, 100 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 101 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 102 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 103 { BITVAL_EOT } 104 }}, 105 { 59, 20, RESERVED }, 106 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 107 { BITVAL_EOT } 108 }}, 109 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 110 { BITVAL_EOT } 111 }}, 112 { BITS_EOT } 113 }}, 114 { 0x10000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM4", "GLIU0 P2D Base Mask Descriptor 4", { 115 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 116 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 117 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 118 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 119 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 120 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 121 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 122 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 123 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 124 { BITVAL_EOT } 125 }}, 126 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 127 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 128 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 129 { BITVAL_EOT } 130 }}, 131 { 59, 20, RESERVED }, 132 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 133 { BITVAL_EOT } 134 }}, 135 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 136 { BITVAL_EOT } 137 }}, 138 { BITS_EOT } 139 }}, 140 { 0x10000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM5", "GLIU0 P2D Base Mask Descriptor 5", { 141 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 142 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 143 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 144 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 145 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 146 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 147 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 148 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 149 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 150 { BITVAL_EOT } 151 }}, 152 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 153 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 154 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 155 { BITVAL_EOT } 156 }}, 157 { 59, 20, RESERVED }, 158 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 159 { BITVAL_EOT } 160 }}, 161 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 162 { BITVAL_EOT } 163 }}, 164 { BITS_EOT } 165 }}, 166 { 0x10000026, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO0", "GLIU0 P2D Base Mask Offset Descriptor 0", { 167 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 168 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 169 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 170 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 171 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 172 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 173 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 174 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 175 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 176 { BITVAL_EOT } 177 }}, 178 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 179 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 180 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 181 { BITVAL_EOT } 182 }}, 183 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { 184 { BITVAL_EOT } 185 }}, 186 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 187 { BITVAL_EOT } 188 }}, 189 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 190 { BITVAL_EOT } 191 }}, 192 { BITS_EOT } 193 }}, 194 { 0x10000027, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO1", "GLIU0 P2D Base Mask Offset Descriptor 1", { 195 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 196 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 197 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 198 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 199 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 200 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 201 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 202 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 203 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 204 { BITVAL_EOT } 205 }}, 206 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 207 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 208 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 209 { BITVAL_EOT } 210 }}, 211 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { 212 { BITVAL_EOT } 213 }}, 214 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 215 { BITVAL_EOT } 216 }}, 217 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 218 { BITVAL_EOT } 219 }}, 220 { BITS_EOT } 221 }}, 222 { 0x10000028, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R0", "GLIU0 P2D Range Descriptor 0", { 223 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 224 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 225 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 226 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 227 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 228 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 229 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 230 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 231 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 232 { BITVAL_EOT } 233 }}, 234 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 235 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 236 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 237 { BITVAL_EOT } 238 }}, 239 { 59, 20, RESERVED }, 240 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 241 { BITVAL_EOT } 242 }}, 243 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 244 { BITVAL_EOT } 245 }}, 246 { BITS_EOT } 247 }}, 248 { 0x10000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO0", "GLIU0 P2D Range Offset Descriptor 0", { 249 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 250 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 251 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 252 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 253 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 254 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 255 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 256 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 257 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 258 { BITVAL_EOT } 259 }}, 260 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 261 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 262 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 263 { BITVAL_EOT } 264 }}, 265 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { 266 { BITVAL_EOT } 267 }}, 268 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 269 { BITVAL_EOT } 270 }}, 271 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 272 { BITVAL_EOT } 273 }}, 274 { BITS_EOT } 275 }}, 276 { 0x1000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO1", "GLIU0 P2D Range Offset Descriptor 1", { 277 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 278 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 279 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 280 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 281 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 282 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 283 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 284 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 285 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 286 { BITVAL_EOT } 287 }}, 288 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 289 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 290 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 291 { BITVAL_EOT } 292 }}, 293 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { 294 { BITVAL_EOT } 295 }}, 296 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 297 { BITVAL_EOT } 298 }}, 299 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 300 { BITVAL_EOT } 301 }}, 302 { BITS_EOT } 303 }}, 304 { 0x1000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO2", "GLIU0 P2D Range Offset Descriptor 2", { 305 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 306 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 307 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 308 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 309 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 310 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 311 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 312 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 313 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 314 { BITVAL_EOT } 315 }}, 316 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 317 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 318 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 319 { BITVAL_EOT } 320 }}, 321 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { 322 { BITVAL_EOT } 323 }}, 324 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 325 { BITVAL_EOT } 326 }}, 327 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 328 { BITVAL_EOT } 329 }}, 330 { BITS_EOT } 331 }}, 332 { 0x1000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_P2D_SC0", "GLIU0 P2D Swiss Cheese Descriptor 0", { 333 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 334 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 335 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 336 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 337 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 338 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 339 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 340 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 341 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 342 { BITVAL_EOT } 343 }}, 344 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 345 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 346 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 347 { BITVAL_EOT } 348 }}, 349 { 59, 12, RESERVED }, 350 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, { 351 { BITVAL_EOT } 352 }}, 353 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, { 354 { BITVAL_EOT } 355 }}, 356 { 15, 2, RESERVED }, 357 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, { 358 { BITVAL_EOT } 359 }}, 360 { BITS_EOT } 361 }}, 362 { 0x100000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM0", "GLIU0 IOD Base Mask Descriptor 0", { 363 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 364 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 365 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 366 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 367 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 368 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 369 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 370 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 371 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 372 { BITVAL_EOT } 373 }}, 374 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 375 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 376 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 377 { BITVAL_EOT } 378 }}, 379 { 59, 20, RESERVED }, 380 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 381 { BITVAL_EOT } 382 }}, 383 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 384 { BITVAL_EOT } 385 }}, 386 { BITS_EOT } 387 }}, 388 { 0x100000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM1", "GLIU0 IOD Base Mask Descriptor 1", { 389 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 390 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 391 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 392 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 393 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 394 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 395 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 396 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 397 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 398 { BITVAL_EOT } 399 }}, 400 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 401 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 402 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 403 { BITVAL_EOT } 404 }}, 405 { 59, 20, RESERVED }, 406 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 407 { BITVAL_EOT } 408 }}, 409 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 410 { BITVAL_EOT } 411 }}, 412 { BITS_EOT } 413 }}, 414 { 0x100000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM2", "GLIU0 IOD Base Mask Descriptor 2", { 415 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 416 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 417 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 418 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 419 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 420 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 421 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 422 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 423 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 424 { BITVAL_EOT } 425 }}, 426 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 427 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 428 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 429 { BITVAL_EOT } 430 }}, 431 { 59, 20, RESERVED }, 432 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 433 { BITVAL_EOT } 434 }}, 435 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 436 { BITVAL_EOT } 437 }}, 438 { BITS_EOT } 439 }}, 440 { 0x100000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC0", "GLIU0 IOD Swiss Cheese Descriptor 0", { 441 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 442 { BITVAL_EOT } 443 }}, 444 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 445 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 446 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 447 { BITVAL_EOT } 448 }}, 449 { 59, 28, RESERVED }, 450 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 451 { BITVAL_EOT } 452 }}, 453 { 23, 2, RESERVED }, 454 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 455 { BITVAL_EOT } 456 }}, 457 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 458 { BITVAL_EOT } 459 }}, 460 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 461 { BITVAL_EOT } 462 }}, 463 { 2, 3, RESERVED }, 464 { BITS_EOT } 465 }}, 466 { 0x100000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC1", "GLIU0 IOD Swiss Cheese Descriptor 1", { 467 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 468 { BITVAL_EOT } 469 }}, 470 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 471 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 472 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 473 { BITVAL_EOT } 474 }}, 475 { 59, 28, RESERVED }, 476 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 477 { BITVAL_EOT } 478 }}, 479 { 23, 2, RESERVED }, 480 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 481 { BITVAL_EOT } 482 }}, 483 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 484 { BITVAL_EOT } 485 }}, 486 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 487 { BITVAL_EOT } 488 }}, 489 { 2, 3, RESERVED }, 490 { BITS_EOT } 491 }}, 492 { 0x100000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC2", "GLIU0 IOD Swiss Cheese Descriptor 2", { 493 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 494 { BITVAL_EOT } 495 }}, 496 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 497 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 498 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 499 { BITVAL_EOT } 500 }}, 501 { 59, 28, RESERVED }, 502 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 503 { BITVAL_EOT } 504 }}, 505 { 23, 2, RESERVED }, 506 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 507 { BITVAL_EOT } 508 }}, 509 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 510 { BITVAL_EOT } 511 }}, 512 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 513 { BITVAL_EOT } 514 }}, 515 { 2, 3, RESERVED }, 516 { BITS_EOT } 517 }}, 518 { 0x100000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC3", "GLIU0 IOD Swiss Cheese Descriptor 3", { 519 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 520 { BITVAL_EOT } 521 }}, 522 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 523 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 524 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 525 { BITVAL_EOT } 526 }}, 527 { 59, 28, RESERVED }, 528 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 529 { BITVAL_EOT } 530 }}, 531 { 23, 2, RESERVED }, 532 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 533 { BITVAL_EOT } 534 }}, 535 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 536 { BITVAL_EOT } 537 }}, 538 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 539 { BITVAL_EOT } 540 }}, 541 { 2, 3, RESERVED }, 542 { BITS_EOT } 543 }}, 544 { 0x100000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC4", "GLIU0 IOD Swiss Cheese Descriptor 4", { 545 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 546 { BITVAL_EOT } 547 }}, 548 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 549 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 550 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 551 { BITVAL_EOT } 552 }}, 553 { 59, 28, RESERVED }, 554 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 555 { BITVAL_EOT } 556 }}, 557 { 23, 2, RESERVED }, 558 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 559 { BITVAL_EOT } 560 }}, 561 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 562 { BITVAL_EOT } 563 }}, 564 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 565 { BITVAL_EOT } 566 }}, 567 { 2, 3, RESERVED }, 568 { BITS_EOT } 569 }}, 570 { 0x100000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC5", "GLIU0 IOD Swiss Cheese Descriptor 5", { 571 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 572 { BITVAL_EOT } 573 }}, 574 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 575 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 576 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 577 { BITVAL_EOT } 578 }}, 579 { 59, 28, RESERVED }, 580 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 581 { BITVAL_EOT } 582 }}, 583 { 23, 2, RESERVED }, 584 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 585 { BITVAL_EOT } 586 }}, 587 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 588 { BITVAL_EOT } 589 }}, 590 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 591 { BITVAL_EOT } 592 }}, 593 { 2, 3, RESERVED }, 594 { BITS_EOT } 595 }}, 596 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", { 597 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, { 598 { MSR1(0), "Reserved" }, 599 { MSR1(1), "8 MB" }, 600 { MSR1(2), "16 MB" }, 601 { MSR1(3), "32 MB" }, 602 { MSR1(4), "64 MB" }, 603 { MSR1(5), "128 MB" }, 604 { MSR1(6), "256 MB" }, 605 { MSR1(7), "512 MB" }, 606 { MSR1(8), "Reserved" }, 607 { MSR1(9), "Reserved" }, 608 { MSR1(10), "Reserved" }, 609 { MSR1(11), "Reserved" }, 610 { MSR1(12), "Reserved" }, 611 { MSR1(13), "Reserved" }, 612 { MSR1(14), "Reserved" }, 613 { MSR1(15), "Reserved" }, 614 { BITVAL_EOT } 615 }}, 616 { 59, 3, RESERVED }, 617 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, { 618 { MSR1(0), "1 Module bank" }, 619 { MSR1(1), "2 Module banks" }, 620 { BITVAL_EOT } 621 }}, 622 { 55, 3, RESERVED }, 623 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, { 624 { MSR1(0), "2 Component banks" }, 625 { MSR1(1), "4 Component banks" }, 626 { BITVAL_EOT } 627 }}, 628 { 51, 1, RESERVED }, 629 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, { 630 { MSR1(0), "1 KB" }, 631 { MSR1(1), "2 KB" }, 632 { MSR1(2), "4 KB" }, 633 { MSR1(3), "8 KB" }, 634 { MSR1(4), "16 KB" }, 635 { MSR1(5), "Reserved" }, 636 { MSR1(6), "Reserved" }, 637 { MSR1(7), "DIMM1 Not Installed" }, 638 { BITVAL_EOT } 639 }}, 640 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, { 641 { MSR1(0), "Reserved" }, 642 { MSR1(1), "8 MB" }, 643 { MSR1(2), "16 MB" }, 644 { MSR1(3), "32 MB" }, 645 { MSR1(4), "64 MB" }, 646 { MSR1(5), "128 MB" }, 647 { MSR1(6), "256 MB" }, 648 { MSR1(7), "512 MB" }, 649 { MSR1(8), "Reserved" }, 650 { MSR1(9), "Reserved" }, 651 { MSR1(10), "Reserved" }, 652 { MSR1(11), "Reserved" }, 653 { MSR1(12), "Reserved" }, 654 { MSR1(13), "Reserved" }, 655 { MSR1(14), "Reserved" }, 656 { MSR1(15), "Reserved" }, 657 { BITVAL_EOT } 658 }}, 659 { 43, 3, RESERVED }, 660 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, { 661 { MSR1(0), "1 Module bank" }, 662 { MSR1(1), "2 Module banks" }, 663 { BITVAL_EOT } 664 }}, 665 { 39, 3, RESERVED }, 666 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, { 667 { MSR1(0), "2 Component banks" }, 668 { MSR1(1), "4 Component banks" }, 669 { BITVAL_EOT } 670 }}, 671 { 35, 1, RESERVED }, 672 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, { 673 { MSR1(0), "1 KB" }, 674 { MSR1(1), "2 KB" }, 675 { MSR1(2), "4 KB" }, 676 { MSR1(3), "8 KB" }, 677 { MSR1(4), "16 KB" }, 678 { MSR1(5), "Reserved" }, 679 { MSR1(6), "Reserved" }, 680 { MSR1(7), "DIMM0 Not Installed" }, 681 { BITVAL_EOT } 682 }}, 683 { 31, 2, RESERVED }, 684 { 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, { 685 { MSR1(0), "Program the DIMM Mode Register" }, 686 { MSR1(1), "Program the DIMM Extended Mode Register" }, 687 { MSR1(2), "Reserved" }, 688 { MSR1(3), "Reserved" }, 689 { BITVAL_EOT } 690 }}, 691 { 27, 1, RESERVED }, 692 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, { 693 { MSR1(0), "Enable" }, 694 { MSR1(1), "Disable" }, 695 { BITVAL_EOT } 696 }}, 697 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, { 698 { MSR1(0), "Normal" }, 699 { MSR1(1), "Reduced" }, 700 { BITVAL_EOT } 701 }}, 702 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, { 703 { MSR1(0), "Enable" }, 704 { MSR1(1), "Disable" }, 705 { BITVAL_EOT } 706 }}, 707 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS }, 708 { 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, { 709 { MSR1(0), "4 SDRAM Clks" }, 710 { MSR1(1), "1 SDRAM Clks" }, 711 { MSR1(2), "2 SDRAM Clks" }, 712 { MSR1(3), "3 SDRAM Clks" }, 713 { BITVAL_EOT } 714 }}, 715 { 5, 2, RESERVED }, 716 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS }, 717 { 2, 1, RESERVED }, 718 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS }, 719 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS }, 720 { BITS_EOT } 721 }}, 722 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", { 723 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS }, 724 { 55, 3, RESERVED }, 725 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, { 726 { MSR1(0), "ADDR[18]" }, 727 { MSR1(1), "ADDR[19]" }, 728 { MSR1(2), "ADDR[20]" }, 729 { MSR1(3), "ADDR[21]" }, 730 { BITVAL_EOT } 731 }}, 732 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, { 733 { MSR1(0), "Disabled" }, 734 { MSR1(1), "Enabled" }, 735 { BITVAL_EOT } 736 }}, 737 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, { 738 { MSR1(0), "Disabled" }, 739 { MSR1(1), "Enabled" }, 740 { BITVAL_EOT } 741 }}, 742 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, { 743 { MSR1(0), "Disabled" }, 744 { MSR1(1), "Enabled" }, 745 { BITVAL_EOT } 746 }}, 747 { 47, 8, RESERVED }, 748 { 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, { 749 { MSR1(0), "Enable" }, 750 { MSR1(1), "Disable" }, 751 { BITVAL_EOT } 752 }}, 753 { 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, { 754 { MSR1(0), "Enable" }, 755 { MSR1(1), "Disable" }, 756 { BITVAL_EOT } 757 }}, 758 { 37, 4, RESERVED }, 759 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, { 760 { MSR1(0), "Low Order Interleave" }, 761 { MSR1(1), "High Order Interleave" }, 762 { BITVAL_EOT } 763 }}, 764 { 32, 1, RESERVED }, 765 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS }, 766 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, { 767 { MSR1(0), "Reserved" }, 768 { MSR1(1), "Reserved" }, 769 { MSR1(2), "2 Clks" }, 770 { MSR1(3), "Reserved" }, 771 { MSR1(4), "Reserved" }, 772 { MSR1(5), "1.5 Clks" }, 773 { MSR1(6), "2.5 Clks" }, 774 { MSR1(7), "Reserved" }, 775 { BITVAL_EOT } 776 }}, 777 { 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, { 778 { MSR1(0), "Reserved" }, 779 { MSR1(1), "1 Clks" }, 780 { MSR1(2), "2 Clks" }, 781 { MSR1(3), "3 Clks" }, 782 { MSR1(4), "4 Clks" }, 783 { MSR1(5), "5 Clks" }, 784 { MSR1(6), "7 Clks" }, 785 { MSR1(7), "8 Clks" }, 786 { MSR1(8), "9 Clks" }, 787 { MSR1(9), "10 Clks" }, 788 { MSR1(10), "11 Clks" }, 789 { MSR1(11), "12 Clks" }, 790 { MSR1(12), "13 Clks" }, 791 { MSR1(13), "14 Clks" }, 792 { MSR1(14), "15 Clks" }, 793 { MSR1(15), "16 Clks" }, 794 { BITVAL_EOT } 795 }}, 796 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, { 797 { MSR1(0), "Reserved" }, 798 { MSR1(1), "1 Clks" }, 799 { MSR1(2), "2 Clks" }, 800 { MSR1(3), "3 Clks" }, 801 { MSR1(4), "4 Clks" }, 802 { MSR1(5), "5 Clks" }, 803 { MSR1(6), "7 Clks" }, 804 { MSR1(7), "8 Clks" }, 805 { MSR1(8), "9 Clks" }, 806 { MSR1(9), "10 Clks" }, 807 { MSR1(10), "11 Clks" }, 808 { MSR1(11), "12 Clks" }, 809 { MSR1(12), "13 Clks" }, 810 { MSR1(13), "14 Clks" }, 811 { MSR1(14), "15 Clks" }, 812 { MSR1(15), "16 Clks" }, 813 { BITVAL_EOT } 814 }}, 815 { 19, 1, RESERVED }, 816 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, { 817 { MSR1(0), "Reserved" }, 818 { MSR1(1), "1 Clks" }, 819 { MSR1(2), "2 Clks" }, 820 { MSR1(3), "3 Clks" }, 821 { MSR1(4), "4 Clks" }, 822 { MSR1(5), "5 Clks" }, 823 { MSR1(6), "6 Clks" }, 824 { MSR1(7), "7 Clks" }, 825 { BITVAL_EOT } 826 }}, 827 { 15, 1, RESERVED }, 828 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, { 829 { MSR1(0), "Reserved" }, 830 { MSR1(1), "1 Clks" }, 831 { MSR1(2), "2 Clks" }, 832 { MSR1(3), "3 Clks" }, 833 { MSR1(4), "4 Clks" }, 834 { MSR1(5), "5 Clks" }, 835 { MSR1(6), "6 Clks" }, 836 { MSR1(7), "Reserved" }, 837 { BITVAL_EOT } 838 }}, 839 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, { 840 { MSR1(0), "Reserved" }, 841 { MSR1(1), "1 Clks" }, 842 { MSR1(2), "2 Clks" }, 843 { MSR1(3), "3 Clks" }, 844 { MSR1(4), "4 Clks" }, 845 { MSR1(5), "5 Clks" }, 846 { MSR1(6), "6 Clks" }, 847 { MSR1(7), "7 Clks" }, 848 { MSR1(8), "Reserved" }, 849 { MSR1(9), "Reserved" }, 850 { MSR1(10), "Reserved" }, 851 { MSR1(11), "Reserved" }, 852 { MSR1(12), "Reserved" }, 853 { MSR1(13), "Reserved" }, 854 { MSR1(14), "Reserved" }, 855 { MSR1(15), "Reserved" }, 856 { BITVAL_EOT } 857 }}, 858 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, { 859 { MSR1(0), "Invalid value" }, 860 { MSR1(1), "1 Clks" }, 861 { MSR1(2), "2 Clks" }, 862 { MSR1(3), "3 Clks" }, 863 { BITVAL_EOT } 864 }}, 865 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, { 866 { MSR1(0), "Invalid value" }, 867 { MSR1(1), "1 Clks" }, 868 { MSR1(2), "2 Clks" }, 869 { MSR1(3), "3 Clks" }, 870 { BITVAL_EOT } 871 }}, 872 { 3, 1, RESERVED }, 873 { 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, { 874 { MSR1(0), "Reserved" }, 875 { MSR1(1), "1 clks" }, 876 { MSR1(2), "2 Clks" }, 877 { MSR1(3), "3 Clks" }, 878 { MSR1(4), "4 Clks" }, 879 { MSR1(5), "5 Clks" }, 880 { MSR1(6), "6 Clks" }, 881 { MSR1(7), "7 Clks" }, 882 { BITVAL_EOT } 883 }}, 884 { BITS_EOT } 885 }}, 886 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", { 887 { 63, 55, RESERVED }, 888 { 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, { 889 { MSR1(0), "No delay" }, 890 { MSR1(1), "Enable delay" }, 891 { BITVAL_EOT } 892 }}, 893 { 7, 5, RESERVED }, 894 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, { 895 { MSR1(0), "Reserved" }, 896 { MSR1(1), "Value when unbuffered DDR SDRAMs are used" }, 897 { MSR1(2), "Value when registered DDR SDRAMs are used" }, 898 { MSR1(3), "Reserved" }, 899 { BITVAL_EOT } 900 }}, 901 { BITS_EOT } 902 }}, 903 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", { 904 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS }, 905 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS }, 906 { BITS_EOT } 907 }}, 908 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", { 909 { 63, 28, RESERVED }, 910 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, { 911 { MSR1(0), "Counter 1 counts" }, 912 { MSR1(1), "Stop Counter" }, 913 { BITVAL_EOT } 914 }}, 915 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, { 916 { MSR1(0), "Do nothing" }, 917 { MSR1(1), "Reset counter 1" }, 918 { BITVAL_EOT } 919 }}, 920 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, { 921 { MSR1(0), "Counter 0 counts" }, 922 { MSR1(1), "Stop counter 0" }, 923 { BITVAL_EOT } 924 }}, 925 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, { 926 { MSR1(0), "Do nothing" }, 927 { MSR1(1), "Reset counter 0" }, 928 { BITVAL_EOT } 929 }}, 930 { 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS }, 931 { 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS }, 932 { 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS }, 933 { 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS }, 934 { BITS_EOT } 935 }}, 936 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", { 937 { 63, 29, RESERVED }, 938 { 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, { 939 { MSR1(0), "Allow back-to-back commands" }, 940 { MSR1(1), "Disable back-to-back commands" }, 941 { BITVAL_EOT } 942 }}, 943 { 33, 1, RESERVED }, 944 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, { 945 { MSR1(0), "Disable" }, 946 { MSR1(1), "Enable" }, 947 { BITVAL_EOT } 948 }}, 949 { 31, 22, RESERVED }, 950 { 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, { 951 { MSR1(0), "CKE1 output enable unmasked" }, 952 { MSR1(1), "CKE1 output enable masked" }, 953 { BITVAL_EOT } 954 }}, 955 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, { 956 { MSR1(0), "CKE0 output enable unmasked" }, 957 { MSR1(1), "CKE0 output enable masked" }, 958 { BITVAL_EOT } 959 }}, 960 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, { 961 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" }, 962 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" }, 963 { BITVAL_EOT } 964 }}, 965 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, { 966 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" }, 967 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" }, 968 { BITVAL_EOT } 969 }}, 970 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, { 971 { MSR1(0), "MA and BA output enable unmasked" }, 972 { MSR1(1), "MA and BA output enable masked" }, 973 { BITVAL_EOT } 974 }}, 975 { 4, 5, RESERVED }, 976 { BITS_EOT } 977 }}, 978 { 0x40000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM0", "GLIU1 P2D Base Mask Descriptor 0", { 979 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 980 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 981 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 982 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 983 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 984 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 985 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 986 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 987 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 988 { BITVAL_EOT } 989 }}, 990 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 991 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 992 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 993 { BITVAL_EOT } 994 }}, 995 { 59, 20, RESERVED }, 996 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 997 { BITVAL_EOT } 998 }}, 999 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1000 { BITVAL_EOT } 1001 }}, 1002 { BITS_EOT } 1003 }}, 1004 { 0x40000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM1", "GLIU1 P2D Base Mask Descriptor 1", { 1005 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1006 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1007 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1008 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1009 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1010 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1011 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1012 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1013 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1014 { BITVAL_EOT } 1015 }}, 1016 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1017 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1018 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1019 { BITVAL_EOT } 1020 }}, 1021 { 59, 20, RESERVED }, 1022 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1023 { BITVAL_EOT } 1024 }}, 1025 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1026 { BITVAL_EOT } 1027 }}, 1028 { BITS_EOT } 1029 }}, 1030 { 0x40000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM2", "GLIU1 P2D Base Mask Descriptor 2", { 1031 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1032 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1033 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1034 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1035 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1036 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1037 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1038 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1039 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1040 { BITVAL_EOT } 1041 }}, 1042 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1043 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1044 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1045 { BITVAL_EOT } 1046 }}, 1047 { 59, 20, RESERVED }, 1048 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1049 { BITVAL_EOT } 1050 }}, 1051 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1052 { BITVAL_EOT } 1053 }}, 1054 { BITS_EOT } 1055 }}, 1056 { 0x40000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM3", "GLIU1 P2D Base Mask Descriptor 3", { 1057 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1058 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1059 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1060 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1061 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1062 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1063 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1064 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1065 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1066 { BITVAL_EOT } 1067 }}, 1068 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1069 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1070 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1071 { BITVAL_EOT } 1072 }}, 1073 { 59, 20, RESERVED }, 1074 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1075 { BITVAL_EOT } 1076 }}, 1077 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1078 { BITVAL_EOT } 1079 }}, 1080 { BITS_EOT } 1081 }}, 1082 { 0x40000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM4", "GLIU1 P2D Base Mask Descriptor 4", { 1083 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1084 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1085 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1086 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1087 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1088 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1089 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1090 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1091 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1092 { BITVAL_EOT } 1093 }}, 1094 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1095 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1096 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1097 { BITVAL_EOT } 1098 }}, 1099 { 59, 20, RESERVED }, 1100 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1101 { BITVAL_EOT } 1102 }}, 1103 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1104 { BITVAL_EOT } 1105 }}, 1106 { BITS_EOT } 1107 }}, 1108 { 0x40000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM5", "GLIU1 P2D Base Mask Descriptor 5", { 1109 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1110 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1111 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1112 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1113 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1114 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1115 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1116 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1117 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1118 { BITVAL_EOT } 1119 }}, 1120 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1121 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1122 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1123 { BITVAL_EOT } 1124 }}, 1125 { 59, 20, RESERVED }, 1126 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1127 { BITVAL_EOT } 1128 }}, 1129 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1130 { BITVAL_EOT } 1131 }}, 1132 { BITS_EOT } 1133 }}, 1134 { 0x40000026, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM6", "GLIU1 P2D Base Mask Descriptor 6", { 1135 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1136 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1137 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1138 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1139 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1140 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1141 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1142 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1143 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1144 { BITVAL_EOT } 1145 }}, 1146 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1147 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1148 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1149 { BITVAL_EOT } 1150 }}, 1151 { 59, 20, RESERVED }, 1152 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1153 { BITVAL_EOT } 1154 }}, 1155 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1156 { BITVAL_EOT } 1157 }}, 1158 { BITS_EOT } 1159 }}, 1160 { 0x40000027, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM7", "GLIU1 P2D Base Mask Descriptor 7", { 1161 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1162 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1163 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1164 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1165 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1166 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1167 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1168 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1169 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1170 { BITVAL_EOT } 1171 }}, 1172 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1173 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1174 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1175 { BITVAL_EOT } 1176 }}, 1177 { 59, 20, RESERVED }, 1178 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1179 { BITVAL_EOT } 1180 }}, 1181 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1182 { BITVAL_EOT } 1183 }}, 1184 { BITS_EOT } 1185 }}, 1186 { 0x40000028, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM8", "GLIU1 P2D Base Mask Descriptor 8", { 1187 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1188 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1189 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1190 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1191 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1192 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1193 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1194 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1195 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1196 { BITVAL_EOT } 1197 }}, 1198 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1199 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1200 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1201 { BITVAL_EOT } 1202 }}, 1203 { 59, 20, RESERVED }, 1204 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { 1205 { BITVAL_EOT } 1206 }}, 1207 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { 1208 { BITVAL_EOT } 1209 }}, 1210 { BITS_EOT } 1211 }}, 1212 { 0x40000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R0", "GLIU0 P2D Range Descriptor 0", { 1213 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1214 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1215 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1216 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1217 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1218 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1219 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1220 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1221 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1222 { BITVAL_EOT } 1223 }}, 1224 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1225 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1226 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1227 { BITVAL_EOT } 1228 }}, 1229 { 59, 20, RESERVED }, 1230 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 1231 { BITVAL_EOT } 1232 }}, 1233 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 1234 { BITVAL_EOT } 1235 }}, 1236 { BITS_EOT } 1237 }}, 1238 { 0x4000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R1", "GLIU0 P2D Range Descriptor 1", { 1239 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1240 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1241 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1242 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1243 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1244 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1245 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1246 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1247 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1248 { BITVAL_EOT } 1249 }}, 1250 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1251 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1252 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1253 { BITVAL_EOT } 1254 }}, 1255 { 59, 20, RESERVED }, 1256 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 1257 { BITVAL_EOT } 1258 }}, 1259 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 1260 { BITVAL_EOT } 1261 }}, 1262 { BITS_EOT } 1263 }}, 1264 { 0x4000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R2", "GLIU0 P2D Range Descriptor 2", { 1265 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1266 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1267 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1268 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1269 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1270 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1271 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1272 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1273 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1274 { BITVAL_EOT } 1275 }}, 1276 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1277 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1278 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1279 { BITVAL_EOT } 1280 }}, 1281 { 59, 20, RESERVED }, 1282 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 1283 { BITVAL_EOT } 1284 }}, 1285 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 1286 { BITVAL_EOT } 1287 }}, 1288 { BITS_EOT } 1289 }}, 1290 { 0x4000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R3", "GLIU0 P2D Range Descriptor 3", { 1291 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1292 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1293 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1294 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1295 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1296 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1297 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1298 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1299 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1300 { BITVAL_EOT } 1301 }}, 1302 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1303 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1304 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1305 { BITVAL_EOT } 1306 }}, 1307 { 59, 20, RESERVED }, 1308 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { 1309 { BITVAL_EOT } 1310 }}, 1311 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { 1312 { BITVAL_EOT } 1313 }}, 1314 { BITS_EOT } 1315 }}, 1316 { 0x4000002D, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_P2D_SC0", "GLIU1 P2D Swiss Cheese Descriptor 0", { 1317 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { 1318 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1319 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1320 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1321 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1322 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1323 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1324 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1325 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1326 { BITVAL_EOT } 1327 }}, 1328 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1329 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1330 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1331 { BITVAL_EOT } 1332 }}, 1333 { 59, 12, RESERVED }, 1334 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, { 1335 { BITVAL_EOT } 1336 }}, 1337 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, { 1338 { BITVAL_EOT } 1339 }}, 1340 { 15, 2, RESERVED }, 1341 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, { 1342 { BITVAL_EOT } 1343 }}, 1344 { BITS_EOT } 1345 }}, 1346 { 0x400000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM0", "GLIU1 IOD Base Mask Descriptor 0", { 1347 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 1348 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1349 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1350 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1351 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1352 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1353 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1354 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1355 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1356 { BITVAL_EOT } 1357 }}, 1358 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1359 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1360 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1361 { BITVAL_EOT } 1362 }}, 1363 { 59, 20, RESERVED }, 1364 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 1365 { BITVAL_EOT } 1366 }}, 1367 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 1368 { BITVAL_EOT } 1369 }}, 1370 { BITS_EOT } 1371 }}, 1372 { 0x400000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM1", "GLIU1 IOD Base Mask Descriptor 1", { 1373 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 1374 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1375 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1376 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1377 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1378 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1379 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1380 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1381 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1382 { BITVAL_EOT } 1383 }}, 1384 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1385 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1386 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1387 { BITVAL_EOT } 1388 }}, 1389 { 59, 20, RESERVED }, 1390 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 1391 { BITVAL_EOT } 1392 }}, 1393 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 1394 { BITVAL_EOT } 1395 }}, 1396 { BITS_EOT } 1397 }}, 1398 { 0x400000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM2", "GLIU1 IOD Base Mask Descriptor 2", { 1399 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { 1400 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, 1401 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, 1402 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, 1403 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, 1404 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, 1405 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, 1406 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, 1407 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, 1408 { BITVAL_EOT } 1409 }}, 1410 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1411 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1412 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1413 { BITVAL_EOT } 1414 }}, 1415 { 59, 20, RESERVED }, 1416 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { 1417 { BITVAL_EOT } 1418 }}, 1419 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { 1420 { BITVAL_EOT } 1421 }}, 1422 { BITS_EOT } 1423 }}, 1424 { 0x400000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC0", "GLIU1 IOD Swiss Cheese Descriptor 0", { 1425 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1426 { BITVAL_EOT } 1427 }}, 1428 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1429 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1430 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1431 { BITVAL_EOT } 1432 }}, 1433 { 59, 28, RESERVED }, 1434 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1435 { BITVAL_EOT } 1436 }}, 1437 { 23, 2, RESERVED }, 1438 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1439 { BITVAL_EOT } 1440 }}, 1441 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1442 { BITVAL_EOT } 1443 }}, 1444 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1445 { BITVAL_EOT } 1446 }}, 1447 { 2, 3, RESERVED }, 1448 { BITS_EOT } 1449 }}, 1450 { 0x400000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC1", "GLIU1 IOD Swiss Cheese Descriptor 1", { 1451 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1452 { BITVAL_EOT } 1453 }}, 1454 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1455 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1456 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1457 { BITVAL_EOT } 1458 }}, 1459 { 59, 28, RESERVED }, 1460 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1461 { BITVAL_EOT } 1462 }}, 1463 { 23, 2, RESERVED }, 1464 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1465 { BITVAL_EOT } 1466 }}, 1467 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1468 { BITVAL_EOT } 1469 }}, 1470 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1471 { BITVAL_EOT } 1472 }}, 1473 { 2, 3, RESERVED }, 1474 { BITS_EOT } 1475 }}, 1476 { 0x400000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC2", "GLIU1 IOD Swiss Cheese Descriptor 2", { 1477 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1478 { BITVAL_EOT } 1479 }}, 1480 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1481 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1482 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1483 { BITVAL_EOT } 1484 }}, 1485 { 59, 28, RESERVED }, 1486 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1487 { BITVAL_EOT } 1488 }}, 1489 { 23, 2, RESERVED }, 1490 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1491 { BITVAL_EOT } 1492 }}, 1493 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1494 { BITVAL_EOT } 1495 }}, 1496 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1497 { BITVAL_EOT } 1498 }}, 1499 { 2, 3, RESERVED }, 1500 { BITS_EOT } 1501 }}, 1502 { 0x400000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC3", "GLIU1 IOD Swiss Cheese Descriptor 3", { 1503 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1504 { BITVAL_EOT } 1505 }}, 1506 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1507 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1508 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1509 { BITVAL_EOT } 1510 }}, 1511 { 59, 28, RESERVED }, 1512 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1513 { BITVAL_EOT } 1514 }}, 1515 { 23, 2, RESERVED }, 1516 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1517 { BITVAL_EOT } 1518 }}, 1519 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1520 { BITVAL_EOT } 1521 }}, 1522 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1523 { BITVAL_EOT } 1524 }}, 1525 { 2, 3, RESERVED }, 1526 { BITS_EOT } 1527 }}, 1528 { 0x400000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC4", "GLIU1 IOD Swiss Cheese Descriptor 4", { 1529 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1530 { BITVAL_EOT } 1531 }}, 1532 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1533 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1534 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1535 { BITVAL_EOT } 1536 }}, 1537 { 59, 28, RESERVED }, 1538 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1539 { BITVAL_EOT } 1540 }}, 1541 { 23, 2, RESERVED }, 1542 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1543 { BITVAL_EOT } 1544 }}, 1545 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1546 { BITVAL_EOT } 1547 }}, 1548 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1549 { BITVAL_EOT } 1550 }}, 1551 { 2, 3, RESERVED }, 1552 { BITS_EOT } 1553 }}, 1554 { 0x400000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC5", "GLIU1 IOD Swiss Cheese Descriptor 5", { 1555 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { 1556 { BITVAL_EOT } 1557 }}, 1558 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { 1559 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, 1560 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, 1561 { BITVAL_EOT } 1562 }}, 1563 { 59, 28, RESERVED }, 1564 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { 1565 { BITVAL_EOT } 1566 }}, 1567 { 23, 2, RESERVED }, 1568 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { 1569 { BITVAL_EOT } 1570 }}, 1571 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { 1572 { BITVAL_EOT } 1573 }}, 1574 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { 1575 { BITVAL_EOT } 1576 }}, 1577 { 2, 3, RESERVED }, 1578 { BITS_EOT } 1579 }}, 1580 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", { 1581 { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, { 1582 { MSR1(0), "Use default values" }, 1583 { MSR1(1), "Use value in bits [62:0]" }, 1584 { BITVAL_EOT } 1585 }}, 1586 { 62, 2, RESERVED }, 1587 { 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS }, 1588 { 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS }, 1589 { 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS }, 1590 { 45, 5, RESERVED}, 1591 { 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS }, 1592 { 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS }, 1593 { 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS }, 1594 { 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS }, 1595 { 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS }, 1596 { 15, 9, RESERVED}, 1597 { 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, { 1598 { MSR1(0), "No Delay" }, 1599 { MSR1(1), "Delay" }, 1600 { BITVAL_EOT } 1601 }}, 1602 { 5, 2, RESERVED }, 1603 { 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS }, 1604 { 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS }, 1605 { BITS_EOT } 1606 }}, 1607 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", { 1608 { 63, 19, RESERVED }, 1609 { 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, { 1610 { MSR1(0), "Divide by 2" }, 1611 { MSR1(1), "Divide by 3" }, 1612 { MSR1(2), "Divide by 4" }, 1613 { MSR1(3), "Divide by 5" }, 1614 { MSR1(4), "Divide by 6" }, 1615 { MSR1(5), "Divide by 7" }, 1616 { MSR1(6), "Divide by 8" }, 1617 { MSR1(7), "Divide by 9" }, 1618 { MSR1(8), "Divide by 10" }, 1619 { MSR1(9), "Divide by 11" }, 1620 { MSR1(10), "Divide by 12" }, 1621 { MSR1(11), "Divide by 13" }, 1622 { MSR1(12), "Divide by 14" }, 1623 { MSR1(13), "Divide by 15" }, 1624 { MSR1(14), "Divide by 16" }, 1625 { MSR1(15), "Divide by 17" }, 1626 { BITVAL_EOT } 1627 }}, 1628 { 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, { 1629 { MSR1(0), "Divide by 2" }, 1630 { MSR1(1), "Divide by 3" }, 1631 { MSR1(2), "Divide by 4" }, 1632 { MSR1(3), "Divide by 5" }, 1633 { MSR1(4), "Divide by 6" }, 1634 { MSR1(5), "Divide by 7" }, 1635 { MSR1(6), "Divide by 8" }, 1636 { MSR1(7), "Divide by 9" }, 1637 { BITVAL_EOT } 1638 }}, 1639 { 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS }, 1640 { 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS }, 1641 { 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, { 1642 { MSR1(1), "PLL locked" }, 1643 { MSR1(0), "PLL is not locked" }, 1644 { BITVAL_EOT } 1645 }}, 1646 { 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, { 1647 { MSR1(0), "Disable" }, 1648 { MSR1(1), "Enable" }, 1649 { BITVAL_EOT } 1650 }}, 1651 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS }, 1652 { 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, { 1653 { MSR1(0), "Use PLL as Clocksource" }, 1654 { MSR1(1), "Use DOTREF as Clocksource" }, 1655 { BITVAL_EOT } 1656 }}, 1657 { 14, 1, "PD", "Power Down", PRESENT_DEC, { 1658 { MSR1(0), "PLL active" }, 1659 { MSR1(1), "PLL in power down mode" }, 1660 { BITVAL_EOT } 1661 }}, 1662 { 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS }, 1663 { 12, 2, RESERVED }, 1664 { 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, { 1665 { MSR1(0), "DDR communication enabled" }, 1666 { MSR1(1), "Reserved" }, 1667 { BITVAL_EOT } 1668 }}, 1669 { 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, { 1670 { MSR1(1), "CPU does not use GLIU1 FIFO" }, 1671 { MSR1(0), "The GLIU1 FIFO is used by the CPU" }, 1672 { BITVAL_EOT } 1673 }}, 1674 { 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, { 1675 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" }, 1676 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" }, 1677 { BITVAL_EOT } 1678 }}, 1679 { 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS }, 1680 { 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS }, 1681 { 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS }, 1682 { 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS }, 1683 { 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS }, 1684 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS }, 1685 { BITS_EOT } 1686 }}, 1687 { MSR_EOT } 1688 };