intel_pentium3_early.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include "msrtool.h" 4 5 int intel_pentium3_early_probe(const struct targetdef *target, const struct cpuid_t *id) { 6 return ((VENDOR_INTEL == id->vendor) && 7 (0x6 == id->family) && ( 8 (0x7 == id->model) || 9 (0x8 == id->model) 10 )); 11 } 12 13 const struct msrdef intel_pentium3_early_msrs[] = { 14 {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", { 15 { BITS_EOT } 16 }}, 17 {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", { 18 { BITS_EOT } 19 }}, 20 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { 21 { BITS_EOT } 22 }}, 23 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { 24 { BITS_EOT } 25 }}, 26 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { 27 { BITS_EOT } 28 }}, 29 {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { 30 { BITS_EOT } 31 }}, 32 {0x33, MSRTYPE_RDWR, MSR2(0, 0), "TEST_CTL", "", { 33 { BITS_EOT } 34 }}, 35 {0x88, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D0", "", { 36 { BITS_EOT } 37 }}, 38 {0x89, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D1", "", { 39 { BITS_EOT } 40 }}, 41 {0x8a, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D2", "", { 42 { BITS_EOT } 43 }}, 44 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { 45 { BITS_EOT } 46 }}, 47 {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", { 48 { BITS_EOT } 49 }}, 50 {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", { 51 { BITS_EOT } 52 }}, 53 {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { 54 { BITS_EOT } 55 }}, 56 {0x116, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_ADDR", "", { 57 { BITS_EOT } 58 }}, 59 {0x118, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_DECC", "", { 60 { BITS_EOT } 61 }}, 62 {0x119, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL", "", { 63 { BITS_EOT } 64 }}, 65 {0x11b, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_BUSY", "", { 66 { BITS_EOT } 67 }}, 68 {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { 69 { BITS_EOT } 70 }}, 71 {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { 72 { BITS_EOT } 73 }}, 74 {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { 75 { BITS_EOT } 76 }}, 77 {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { 78 { BITS_EOT } 79 }}, 80 {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { 81 { BITS_EOT } 82 }}, 83 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { 84 { BITS_EOT } 85 }}, 86 {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", { 87 { BITS_EOT } 88 }}, 89 {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL0", "", { 90 { BITS_EOT } 91 }}, 92 {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL1", "", { 93 { BITS_EOT } 94 }}, 95 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { 96 { BITS_EOT } 97 }}, 98 {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCHFROMIP", "", { 99 { BITS_EOT } 100 }}, 101 {0x1dc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCHTOIP", "", { 102 { BITS_EOT } 103 }}, 104 {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTINTFROMIP", "", { 105 { BITS_EOT } 106 }}, 107 {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTINTTOIP", "", { 108 { BITS_EOT } 109 }}, 110 {0x1e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ROB_CR_BKUPTMPDR6", "", { 111 { BITS_EOT } 112 }}, 113 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { 114 { BITS_EOT } 115 }}, 116 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { 117 { BITS_EOT } 118 }}, 119 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { 120 { BITS_EOT } 121 }}, 122 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { 123 { BITS_EOT } 124 }}, 125 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { 126 { BITS_EOT } 127 }}, 128 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { 129 { BITS_EOT } 130 }}, 131 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { 132 { BITS_EOT } 133 }}, 134 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { 135 { BITS_EOT } 136 }}, 137 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { 138 { BITS_EOT } 139 }}, 140 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { 141 { BITS_EOT } 142 }}, 143 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { 144 { BITS_EOT } 145 }}, 146 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { 147 { BITS_EOT } 148 }}, 149 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { 150 { BITS_EOT } 151 }}, 152 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { 153 { BITS_EOT } 154 }}, 155 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { 156 { BITS_EOT } 157 }}, 158 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { 159 { BITS_EOT } 160 }}, 161 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { 162 { BITS_EOT } 163 }}, 164 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { 165 { BITS_EOT } 166 }}, 167 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { 168 { BITS_EOT } 169 }}, 170 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { 171 { BITS_EOT } 172 }}, 173 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { 174 { BITS_EOT } 175 }}, 176 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { 177 { BITS_EOT } 178 }}, 179 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { 180 { BITS_EOT } 181 }}, 182 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { 183 { BITS_EOT } 184 }}, 185 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { 186 { BITS_EOT } 187 }}, 188 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { 189 { BITS_EOT } 190 }}, 191 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { 192 { BITS_EOT } 193 }}, 194 {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { 195 { BITS_EOT } 196 }}, 197 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { 198 { BITS_EOT } 199 }}, 200 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { 201 { BITS_EOT } 202 }}, 203 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { 204 { BITS_EOT } 205 }}, 206 {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { 207 { BITS_EOT } 208 }}, 209 {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { 210 { BITS_EOT } 211 }}, 212 {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { 213 { BITS_EOT } 214 }}, 215 {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { 216 { BITS_EOT } 217 }}, 218 {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { 219 { BITS_EOT } 220 }}, 221 {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { 222 { BITS_EOT } 223 }}, 224 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { 225 { BITS_EOT } 226 }}, 227 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { 228 { BITS_EOT } 229 }}, 230 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { 231 { BITS_EOT } 232 }}, 233 {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { 234 { BITS_EOT } 235 }}, 236 {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { 237 { BITS_EOT } 238 }}, 239 {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { 240 { BITS_EOT } 241 }}, 242 { MSR_EOT } 243 };