intel_pentium4_later.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include "msrtool.h" 4 5 int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) { 6 return ((VENDOR_INTEL == id->vendor) && 7 (0xf == id->family) && ( 8 (0x3 == id->model) || 9 (0x4 == id->model) 10 )); 11 } 12 13 const struct msrdef intel_pentium4_later_msrs[] = { 14 {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", { 15 { BITS_EOT } 16 }}, 17 {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", { 18 { BITS_EOT } 19 }}, 20 {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_LINE_SIZE", "", { 21 { BITS_EOT } 22 }}, 23 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { 24 { BITS_EOT } 25 }}, 26 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { 27 { BITS_EOT } 28 }}, 29 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { 30 { BITS_EOT } 31 }}, 32 {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", { 33 { BITS_EOT } 34 }}, 35 {0x2b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWERON", "", { 36 { BITS_EOT } 37 }}, 38 {0x2c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_FREQUENCY_ID", "", { 39 { BITS_EOT } 40 }}, 41 {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", { 42 { BITS_EOT } 43 }}, 44 {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG", "", { 45 { BITS_EOT } 46 }}, 47 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { 48 { BITS_EOT } 49 }}, 50 {0x9b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SMM_MONITOR_CTL", "", { 51 { BITS_EOT } 52 }}, 53 {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { 54 { BITS_EOT } 55 }}, 56 {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { 57 { BITS_EOT } 58 }}, 59 {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { 60 { BITS_EOT } 61 }}, 62 {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { 63 { BITS_EOT } 64 }}, 65 {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { 66 { BITS_EOT } 67 }}, 68 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { 69 { BITS_EOT } 70 }}, 71 {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", { 72 { BITS_EOT } 73 }}, 74 {0x180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", { 75 { BITS_EOT } 76 }}, 77 {0x181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", { 78 { BITS_EOT } 79 }}, 80 {0x182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", { 81 { BITS_EOT } 82 }}, 83 {0x183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", { 84 { BITS_EOT } 85 }}, 86 {0x184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", { 87 { BITS_EOT } 88 }}, 89 {0x185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", { 90 { BITS_EOT } 91 }}, 92 {0x186, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBP", "", { 93 { BITS_EOT } 94 }}, 95 {0x187, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSP", "", { 96 { BITS_EOT } 97 }}, 98 {0x188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", { 99 { BITS_EOT } 100 }}, 101 {0x189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", { 102 { BITS_EOT } 103 }}, 104 {0x18a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", { 105 { BITS_EOT } 106 }}, 107 {0x18b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED1", "", { 108 { BITS_EOT } 109 }}, 110 {0x18c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED2", "", { 111 { BITS_EOT } 112 }}, 113 {0x18d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED3", "", { 114 { BITS_EOT } 115 }}, 116 {0x18e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED4", "", { 117 { BITS_EOT } 118 }}, 119 {0x18f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED5", "", { 120 { BITS_EOT } 121 }}, 122 {0x190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", { 123 { BITS_EOT } 124 }}, 125 {0x191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", { 126 { BITS_EOT } 127 }}, 128 {0x192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", { 129 { BITS_EOT } 130 }}, 131 {0x193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", { 132 { BITS_EOT } 133 }}, 134 {0x194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", { 135 { BITS_EOT } 136 }}, 137 {0x195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", { 138 { BITS_EOT } 139 }}, 140 {0x196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", { 141 { BITS_EOT } 142 }}, 143 {0x197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", { 144 { BITS_EOT } 145 }}, 146 {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { 147 { BITS_EOT } 148 }}, 149 {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { 150 { BITS_EOT } 151 }}, 152 {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { 153 { BITS_EOT } 154 }}, 155 {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { 156 { BITS_EOT } 157 }}, 158 {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { 159 { BITS_EOT } 160 }}, 161 {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { 162 { BITS_EOT } 163 }}, 164 {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", { 165 { BITS_EOT } 166 }}, 167 {0x1a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PLATFORM_BRV", "", { 168 { BITS_EOT } 169 }}, 170 {0x1d7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", { 171 { BITS_EOT } 172 }}, 173 {0x1d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", { 174 { BITS_EOT } 175 }}, 176 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DEBUGCTLA", "", { 177 { BITS_EOT } 178 }}, 179 {0x1da, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH", "", { 180 { BITS_EOT } 181 }}, 182 {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0", "", { 183 { BITS_EOT } 184 }}, 185 {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2", "", { 186 { BITS_EOT } 187 }}, 188 {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3", "", { 189 { BITS_EOT } 190 }}, 191 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { 192 { BITS_EOT } 193 }}, 194 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { 195 { BITS_EOT } 196 }}, 197 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { 198 { BITS_EOT } 199 }}, 200 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { 201 { BITS_EOT } 202 }}, 203 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { 204 { BITS_EOT } 205 }}, 206 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { 207 { BITS_EOT } 208 }}, 209 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { 210 { BITS_EOT } 211 }}, 212 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { 213 { BITS_EOT } 214 }}, 215 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { 216 { BITS_EOT } 217 }}, 218 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { 219 { BITS_EOT } 220 }}, 221 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { 222 { BITS_EOT } 223 }}, 224 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { 225 { BITS_EOT } 226 }}, 227 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { 228 { BITS_EOT } 229 }}, 230 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { 231 { BITS_EOT } 232 }}, 233 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { 234 { BITS_EOT } 235 }}, 236 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { 237 { BITS_EOT } 238 }}, 239 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { 240 { BITS_EOT } 241 }}, 242 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { 243 { BITS_EOT } 244 }}, 245 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { 246 { BITS_EOT } 247 }}, 248 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { 249 { BITS_EOT } 250 }}, 251 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { 252 { BITS_EOT } 253 }}, 254 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { 255 { BITS_EOT } 256 }}, 257 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { 258 { BITS_EOT } 259 }}, 260 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { 261 { BITS_EOT } 262 }}, 263 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { 264 { BITS_EOT } 265 }}, 266 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { 267 { BITS_EOT } 268 }}, 269 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { 270 { BITS_EOT } 271 }}, 272 {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", { 273 { BITS_EOT } 274 }}, 275 {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { 276 { BITS_EOT } 277 }}, 278 {0x300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", { 279 { BITS_EOT } 280 }}, 281 {0x301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", { 282 { BITS_EOT } 283 }}, 284 {0x302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", { 285 { BITS_EOT } 286 }}, 287 {0x303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", { 288 { BITS_EOT } 289 }}, 290 {0x304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", { 291 { BITS_EOT } 292 }}, 293 {0x305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", { 294 { BITS_EOT } 295 }}, 296 {0x306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", { 297 { BITS_EOT } 298 }}, 299 {0x307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", { 300 { BITS_EOT } 301 }}, 302 {0x308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", { 303 { BITS_EOT } 304 }}, 305 {0x309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", { 306 { BITS_EOT } 307 }}, 308 {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER2", "", { 309 { BITS_EOT } 310 }}, 311 {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", { 312 { BITS_EOT } 313 }}, 314 {0x30c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", { 315 { BITS_EOT } 316 }}, 317 {0x30d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", { 318 { BITS_EOT } 319 }}, 320 {0x30e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", { 321 { BITS_EOT } 322 }}, 323 {0x30f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", { 324 { BITS_EOT } 325 }}, 326 {0x310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", { 327 { BITS_EOT } 328 }}, 329 {0x311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", { 330 { BITS_EOT } 331 }}, 332 {0x360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", { 333 { BITS_EOT } 334 }}, 335 {0x361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", { 336 { BITS_EOT } 337 }}, 338 {0x362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", { 339 { BITS_EOT } 340 }}, 341 {0x363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", { 342 { BITS_EOT } 343 }}, 344 {0x364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", { 345 { BITS_EOT } 346 }}, 347 {0x365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", { 348 { BITS_EOT } 349 }}, 350 {0x366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", { 351 { BITS_EOT } 352 }}, 353 {0x367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", { 354 { BITS_EOT } 355 }}, 356 {0x368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", { 357 { BITS_EOT } 358 }}, 359 {0x369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", { 360 { BITS_EOT } 361 }}, 362 {0x36a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", { 363 { BITS_EOT } 364 }}, 365 {0x36b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", { 366 { BITS_EOT } 367 }}, 368 {0x36c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", { 369 { BITS_EOT } 370 }}, 371 {0x36d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", { 372 { BITS_EOT } 373 }}, 374 {0x36e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", { 375 { BITS_EOT } 376 }}, 377 {0x36f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", { 378 { BITS_EOT } 379 }}, 380 {0x370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", { 381 { BITS_EOT } 382 }}, 383 {0x371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", { 384 { BITS_EOT } 385 }}, 386 {0x3a0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", { 387 { BITS_EOT } 388 }}, 389 {0x3a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", { 390 { BITS_EOT } 391 }}, 392 {0x3a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", { 393 { BITS_EOT } 394 }}, 395 {0x3a3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", { 396 { BITS_EOT } 397 }}, 398 {0x3a4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", { 399 { BITS_EOT } 400 }}, 401 {0x3a5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", { 402 { BITS_EOT } 403 }}, 404 {0x3a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", { 405 { BITS_EOT } 406 }}, 407 {0x3a7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", { 408 { BITS_EOT } 409 }}, 410 {0x3a8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", { 411 { BITS_EOT } 412 }}, 413 {0x3a9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", { 414 { BITS_EOT } 415 }}, 416 {0x3aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", { 417 { BITS_EOT } 418 }}, 419 {0x3ab, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", { 420 { BITS_EOT } 421 }}, 422 {0x3ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", { 423 { BITS_EOT } 424 }}, 425 {0x3ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", { 426 { BITS_EOT } 427 }}, 428 {0x3ae, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", { 429 { BITS_EOT } 430 }}, 431 {0x3af, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", { 432 { BITS_EOT } 433 }}, 434 {0x3b0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", { 435 { BITS_EOT } 436 }}, 437 {0x3b1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", { 438 { BITS_EOT } 439 }}, 440 {0x3b2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", { 441 { BITS_EOT } 442 }}, 443 {0x3b3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", { 444 { BITS_EOT } 445 }}, 446 {0x3b4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", { 447 { BITS_EOT } 448 }}, 449 {0x3b5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR1", "", { 450 { BITS_EOT } 451 }}, 452 {0x3b6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", { 453 { BITS_EOT } 454 }}, 455 {0x3b7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", { 456 { BITS_EOT } 457 }}, 458 {0x3b8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", { 459 { BITS_EOT } 460 }}, 461 {0x3b9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", { 462 { BITS_EOT } 463 }}, 464 {0x3ba, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", { 465 { BITS_EOT } 466 }}, 467 /* MSR_IQ_ESCR1 MSR is not available on later processors. 468 It is only available on processor family 0FH, models 01H-02H */ 469 //{0x3bb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", { 470 // { BITS_EOT } 471 //}}, 472 {0x3bc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", { 473 { BITS_EOT } 474 }}, 475 {0x3bd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", { 476 { BITS_EOT } 477 }}, 478 {0x3be, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", { 479 { BITS_EOT } 480 }}, 481 {0x3c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", { 482 { BITS_EOT } 483 }}, 484 {0x3c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", { 485 { BITS_EOT } 486 }}, 487 {0x3c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", { 488 { BITS_EOT } 489 }}, 490 {0x3c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", { 491 { BITS_EOT } 492 }}, 493 {0x3c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", { 494 { BITS_EOT } 495 }}, 496 {0x3c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", { 497 { BITS_EOT } 498 }}, 499 {0x3c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", { 500 { BITS_EOT } 501 }}, 502 {0x3c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", { 503 { BITS_EOT } 504 }}, 505 {0x3ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", { 506 { BITS_EOT } 507 }}, 508 {0x3cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", { 509 { BITS_EOT } 510 }}, 511 {0x3cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", { 512 { BITS_EOT } 513 }}, 514 {0x3cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", { 515 { BITS_EOT } 516 }}, 517 {0x3e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", { 518 { BITS_EOT } 519 }}, 520 {0x3e1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", { 521 { BITS_EOT } 522 }}, 523 {0x3f0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", { 524 { BITS_EOT } 525 }}, 526 {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", { 527 { BITS_EOT } 528 }}, 529 {0x3f2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", { 530 { BITS_EOT } 531 }}, 532 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { 533 { BITS_EOT } 534 }}, 535 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { 536 { BITS_EOT } 537 }}, 538 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { 539 { BITS_EOT } 540 }}, 541 /* The IA32_MC0_MISC MSR is either not implemented or does 542 not contain additional information if the MISCV flag in 543 the IA32_MC0_STATUS register is clear. When not implemented 544 in the processor, all reads and writes to this MSR will 545 cause a generalprotection exception. */ 546 //{0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", { 547 // { BITS_EOT } 548 //}}, 549 {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { 550 { BITS_EOT } 551 }}, 552 {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { 553 { BITS_EOT } 554 }}, 555 {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { 556 { BITS_EOT } 557 }}, 558 /* The IA32_MC1_MISC MSR is either not implemented or does 559 not contain additional information if the MISCV flag in 560 the IA32_MC1_STATUS register is clear. When not implemented 561 in the processor, all reads and writes to this MSR will 562 cause a generalprotection exception.*/ 563 //{0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", { 564 // { BITS_EOT } 565 //}}, 566 {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { 567 { BITS_EOT } 568 }}, 569 {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { 570 { BITS_EOT } 571 }}, 572 {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { 573 { BITS_EOT } 574 }}, 575 {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", { 576 { BITS_EOT } 577 }}, 578 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { 579 { BITS_EOT } 580 }}, 581 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { 582 { BITS_EOT } 583 }}, 584 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { 585 { BITS_EOT } 586 }}, 587 {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", { 588 { BITS_EOT } 589 }}, 590 {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { 591 { BITS_EOT } 592 }}, 593 {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { 594 { BITS_EOT } 595 }}, 596 {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { 597 { BITS_EOT } 598 }}, 599 {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", { 600 { BITS_EOT } 601 }}, 602 {0x481, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PINBASED_CTLS", "", { 603 { BITS_EOT } 604 }}, 605 {0x482, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS", "", { 606 { BITS_EOT } 607 }}, 608 {0x483, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_EXIT_CTLS", "", { 609 { BITS_EOT } 610 }}, 611 {0x484, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS", "", { 612 { BITS_EOT } 613 }}, 614 {0x485, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_MISC", "", { 615 { BITS_EOT } 616 }}, 617 {0x487, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_CR0_FIXED1", "", { 618 { BITS_EOT } 619 }}, 620 {0x489, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_CR4_FIXED1", "", { 621 { BITS_EOT } 622 }}, 623 {0x48b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", "", { 624 { BITS_EOT } 625 }}, 626 {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", { 627 { BITS_EOT } 628 }}, 629 {0x680, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", { 630 { BITS_EOT } 631 }}, 632 {0x682, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", { 633 { BITS_EOT } 634 }}, 635 {0x684, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "", { 636 { BITS_EOT } 637 }}, 638 {0x686, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "", { 639 { BITS_EOT } 640 }}, 641 {0x688, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_FROM_IP", "", { 642 { BITS_EOT } 643 }}, 644 {0x68a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_FROM_IP", "", { 645 { BITS_EOT } 646 }}, 647 {0x68c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_FROM_IP", "", { 648 { BITS_EOT } 649 }}, 650 {0x68e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_FROM_IP", "", { 651 { BITS_EOT } 652 }}, 653 {0x6c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_IP", "", { 654 { BITS_EOT } 655 }}, 656 {0x6c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_IP", "", { 657 { BITS_EOT } 658 }}, 659 {0x6c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_IP", "", { 660 { BITS_EOT } 661 }}, 662 {0x6c6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_IP", "", { 663 { BITS_EOT } 664 }}, 665 {0x6c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_TO_IP", "", { 666 { BITS_EOT } 667 }}, 668 {0x6ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_TO_IP", "", { 669 { BITS_EOT } 670 }}, 671 {0x6cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_TO_IP", "", { 672 { BITS_EOT } 673 }}, 674 {0x6ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_TO_IP", "", { 675 { BITS_EOT } 676 }}, 677 { MSR_EOT } 678 };