k8.c
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include "msrtool.h" 4 5 int k8_probe(const struct targetdef *target, const struct cpuid_t *id) { 6 return (VENDOR_AMD == id->vendor) && (0xF == id->family); 7 } 8 9 /* 10 * AMD BKDG Publication # 32559 Revision: 3.08 Issue Date: July 2007 11 */ 12 const struct msrdef k8_msrs[] = { 13 { 0xC0000080, MSRTYPE_RDWR, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", { 14 { 63, 32, RESERVED }, 15 { 31, 18, RESERVED }, 16 { 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC, { 17 { MSR1(0), "FXSAVE/FRSTOR disabled" }, 18 { MSR1(1), "FXSAVE/FRSTOR enabled" }, 19 { BITVAL_EOT } 20 }}, 21 { 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC, { 22 { MSR1(0), "Long mode segment limit check disabled" }, 23 { MSR1(1), "Long mode segment limit check enabled" }, 24 { BITVAL_EOT } 25 }}, 26 { 12, 1, "SVME:", "SVM Enable", PRESENT_DEC, { 27 { MSR1(0), "SVM features disabled" }, 28 { MSR1(1), "SVM features enabled" }, 29 { BITVAL_EOT } 30 }}, 31 { 11, 1, "NXE:", "No-Execute Page Enable", PRESENT_DEC, { 32 { MSR1(0), "NXE features disabled" }, 33 { MSR1(1), "NXE features enabled" }, 34 { BITVAL_EOT } 35 }}, 36 { 10, 1, "LMA:", "Long Mode Active", PRESENT_DEC, { 37 { MSR1(0), "Long Mode feature not active" }, 38 { MSR1(1), "Long Mode feature active" }, 39 { BITVAL_EOT } 40 }}, 41 { 9, 1, RESERVED }, 42 { 8, 1, "LME:", "Long Mode Enable", PRESENT_DEC, { 43 { MSR1(0), "Long Mode feature disabled" }, 44 { MSR1(1), "Long Mode feature enabled" }, 45 { BITVAL_EOT } 46 }}, 47 { 7, 7, RESERVED }, 48 { 0, 1, "SYSCALL:", "System Call Extension Enable", PRESENT_DEC, { 49 { MSR1(0), "System Call feature disabled" }, 50 { MSR1(1), "System Call feature enabled" }, 51 { BITVAL_EOT } 52 }}, 53 { BITS_EOT } 54 }}, 55 56 { 0xC0010010, MSRTYPE_RDWR, MSR2(0, 0), "SYSCFG Register", "This register controls the system configuration", { 57 { 63, 32, RESERVED }, 58 { 31, 9, RESERVED }, 59 { 22, 1, "Tom2ForceMemTypeWB:", "Top of Memory 2 Memory Type Write Back", PRESENT_DEC, { 60 { MSR1(0), "Tom2ForceMemTypeWB disabled" }, 61 { MSR1(1), "Tom2ForceMemTypeWB enabled" }, 62 { BITVAL_EOT } 63 }}, 64 { 21, 1, "MtrrTom2En:", "Top of Memory Address Register 2 Enable", PRESENT_DEC, { 65 { MSR1(0), "MtrrTom2En disabled" }, 66 { MSR1(1), "MtrrTom2En enabled" }, 67 { BITVAL_EOT } 68 }}, 69 { 20, 1, "MtrrVarDramEn:", "Top of Memory Address Register and I/O Range Register Enable", PRESENT_DEC, { 70 { MSR1(0), "MtrrVarDramEn disabled" }, 71 { MSR1(1), "MtrrVarDramEn enabled" }, 72 { BITVAL_EOT } 73 }}, 74 { 19, 1, "MtrrFixDramModEn:", "RdDram and WrDram Bits Modification Enable", PRESENT_DEC, { 75 { MSR1(0), "MtrrFixDramModEn disabled" }, 76 { MSR1(1), "MtrrFixDramModEn enabled" }, 77 { BITVAL_EOT } 78 }}, 79 { 18, 1, "MtrrFixDramEn:", "Fixed RdDram and WrDram Attributes Enable", PRESENT_DEC, { 80 { MSR1(0), "MtrrFixDramEn disabled" }, 81 { MSR1(1), "MtrrFixDramEn enabled" }, 82 { BITVAL_EOT } 83 }}, 84 { 17, 1, "SysUcLockEn:", "System Interface Lock Command Enable", PRESENT_DEC, { 85 { MSR1(0), "SysUcLockEn disabled" }, 86 { MSR1(1), "SysUcLockEn enabled" }, 87 { BITVAL_EOT } 88 }}, 89 { 16, 1, "ChxToDirtyDis:", "Change to Dirty Command Disable", PRESENT_DEC, { 90 { MSR1(0), "ChxToDirtyDis disabled" }, 91 { MSR1(1), "ChxToDirtyDis enabled" }, 92 { BITVAL_EOT } 93 }}, 94 { 15, 5, RESERVED }, 95 { 10, 1, "SetDirtyEnO:", "SharedToDirty Command for O->M State Transition Enable", PRESENT_DEC, { 96 { MSR1(0), "SetDirtyEnO disabled" }, 97 { MSR1(1), "SetDirtyEnO enabled" }, 98 { BITVAL_EOT } 99 }}, 100 { 9, 1, "SetDirtyEnS:", "SharedToDirty Command for S->M State Transition Enable", PRESENT_DEC, { 101 { MSR1(0), "SetDirtyEnS disabled" }, 102 { MSR1(1), "SetDirtyEnS enabled" }, 103 { BITVAL_EOT } 104 }}, 105 { 8, 1, "SetDirtyEnE:", "CleanToDirty Command for E->M State Transition Enable", PRESENT_DEC, { 106 { MSR1(0), "SetDirtyEnE disabled" }, 107 { MSR1(1), "SetDirtyEnE enabled" }, 108 { BITVAL_EOT } 109 }}, 110 { 7, 3, "SysVicLimit:", "Outstanding Victim Bus Command Limit", PRESENT_HEX, { 111 { BITVAL_EOT } 112 }}, 113 { 4, 5, "SysAckLimit:", "Outstanding Bus Command Limit", PRESENT_HEX, { 114 { BITVAL_EOT } 115 }}, 116 { BITS_EOT } 117 }}, 118 119 { 0xC0010015, MSRTYPE_RDWR, MSR2(0, 0), "HWCR Register", "This register controls the hardware configuration", { 120 { 63, 32, RESERVED }, 121 { 31, 2, RESERVED }, 122 { 29, 6, "START_FID:", "Status of the startup FID", PRESENT_HEX, { 123 { BITVAL_EOT } 124 }}, 125 { 23, 5, RESERVED }, 126 { 18, 1, "MCi_STATUS_WREN:", "MCi Status Write Enable", PRESENT_DEC, { 127 { MSR1(0), "MCi_STATUS_WREN disabled" }, 128 { MSR1(1), "MCi_STATUS_WREN enabled" }, 129 { BITVAL_EOT } 130 }}, 131 { 17, 1, "WRAP32DIS:", "32-bit Address Wrap Disable", PRESENT_DEC, { 132 { MSR1(0), "WRAP32DIS clear" }, 133 { MSR1(1), "WRAP32DIS set" }, 134 { BITVAL_EOT } 135 }}, 136 { 16, 1, RESERVED }, 137 { 15, 1, "SSEDIS:", "SSE Instructions Disable", PRESENT_DEC, { 138 { MSR1(0), "SSEDIS clear" }, 139 { MSR1(1), "SSEDIS set" }, 140 { BITVAL_EOT } 141 }}, 142 { 14, 1, "RSMSPCYCDIS:", "Special Bus Cycle On RSM Disable", PRESENT_DEC, { 143 { MSR1(0), "RSMSPCYCDIS clear" }, 144 { MSR1(1), "RSMSPCYCDIS set" }, 145 { BITVAL_EOT } 146 }}, 147 { 13, 1, "SMISPCYCDIS:", "Special Bus Cycle On SMI Disable", PRESENT_DEC, { 148 { MSR1(0), "SMISPCYCDIS clear" }, 149 { MSR1(1), "SMISPCYCDIS set" }, 150 { BITVAL_EOT } 151 }}, 152 { 12, 1, "HLTXSPCYCEN:", "Enable Special Bus Cycle On Exit From HLT", PRESENT_DEC, { 153 { MSR1(0), "HLTXSPCYCEN disabled" }, 154 { MSR1(1), "HLTXSPCYCEN enabled" }, 155 { BITVAL_EOT } 156 }}, 157 { 11, 4, RESERVED }, 158 { 8, 1, "IGNNE_EM:", "IGNNE Port Emulation Enable", PRESENT_DEC, { 159 { MSR1(0), "IGNNE_EM disabled" }, 160 { MSR1(1), "IGNNE_EM enabled" }, 161 { BITVAL_EOT } 162 }}, 163 { 7, 1, "DISLOCK:", "Disable x86 LOCK prefix functionality", PRESENT_DEC, { 164 { MSR1(0), "DISLOCK clear" }, 165 { MSR1(1), "DISLOCK set" }, 166 { BITVAL_EOT } 167 }}, 168 { 6, 1, "FFDIS:", "TLB Flush Filter Disable", PRESENT_DEC, { 169 { MSR1(0), "FFDIS clear" }, 170 { MSR1(1), "FFDIS set" }, 171 { BITVAL_EOT } 172 }}, 173 { 5, 1, RESERVED }, 174 { 4, 1, "INVD_WBINVD:", "INVD to WBINVD Conversion", PRESENT_DEC, { 175 { MSR1(0), "INVD_WBINVD disabled" }, 176 { MSR1(1), "INVD_WBINVD enabled" }, 177 { BITVAL_EOT } 178 }}, 179 { 3, 1, "TLBCACHEDIS:", "TLB Cacheable Memory Disable", PRESENT_DEC, { 180 { MSR1(0), "TLBCACHEDIS clear" }, 181 { MSR1(1), "TLBCACHEDIS set" }, 182 { BITVAL_EOT } 183 }}, 184 { 2, 1, RESERVED }, 185 { 1, 1, "SLOWFENCE:", "Slow SFENCE Enable", PRESENT_DEC, { 186 { MSR1(0), "SLOWFENCE disabled" }, 187 { MSR1(1), "SLOWFENCE enabled" }, 188 { BITVAL_EOT } 189 }}, 190 { 0, 1, "SMMLOCK:", "SMM Configuration Lock", PRESENT_DEC, { 191 { MSR1(0), "SMMLOCK disabled" }, 192 { MSR1(1), "SMMLOCK enabled" }, 193 { BITVAL_EOT } 194 }}, 195 { BITS_EOT } 196 }}, 197 198 { 0xC001001F, MSRTYPE_RDWR, MSR2(0, 0), "NB_CFG Register", "", { 199 { 63, 9, RESERVED }, 200 { 54, 1, "InitApicIdCpuIdLo:", "CpuId and NodeId[2:0] bit field positions are swapped in the APICID", PRESENT_DEC, { 201 { MSR1(0), "CpuId and NodeId not swapped" }, 202 { MSR1(1), "CpuId and NodeId swapped" }, 203 { BITVAL_EOT } 204 }}, 205 { 53, 8, RESERVED }, 206 { 45, 1, "DisUsSysMgtRqToNLdt:", "Disable Upstream System Management Rebroadcast", PRESENT_DEC, { 207 { MSR1(0), "Upstream Rebroadcast disabled" }, 208 { MSR1(1), "Upstream Rebroadcast enabled" }, 209 { BITVAL_EOT } 210 }}, 211 { 44, 1, RESERVED }, 212 { 43, 1, "DisThmlPfMonSmiInt:", "Disable Performance Monitor SMI", PRESENT_DEC, { 213 { MSR1(0), "Performance Monitor SMI enabled" }, 214 { MSR1(1), "Performance Monitor SMI disabled" }, 215 { BITVAL_EOT } 216 }}, 217 { 42, 6, RESERVED }, 218 { 36, 1, "DisDatMsk:", "Disables DRAM data masking function", PRESENT_DEC, { 219 { MSR1(0), "DRAM data masking enabled" }, 220 { MSR1(1), "DRAM data masking disabled" }, 221 { BITVAL_EOT } 222 }}, 223 { 35, 4, RESERVED }, 224 { 31, 1, "DisCohLdtCfg:", "Disable Coherent HyperTransport Configuration Accesses", PRESENT_DEC, { 225 { MSR1(0), "Coherent HyperTransport Configuration enabled" }, 226 { MSR1(1), "Coherent HyperTransport Configuration disabled" }, 227 { BITVAL_EOT } 228 }}, 229 { 30, 21, RESERVED }, 230 { 9, 1, "DisRefUseFreeBuf:", "Disable Display Refresh from Using Free List Buffers", PRESENT_DEC, { 231 { MSR1(0), "Display refresh requests enabled" }, 232 { MSR1(1), "Display refresh requests disabled" }, 233 { BITVAL_EOT } 234 }}, 235 { BITS_EOT } 236 }}, 237 238 { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", { 239 { 63, 24, RESERVED }, 240 { 39, 8, "TOM 39-32", "", PRESENT_HEX, { 241 { BITVAL_EOT } 242 }}, 243 { 31, 9, "TOM 31-23", "", PRESENT_HEX, { 244 { BITVAL_EOT } 245 }}, 246 { 22, 23, RESERVED }, 247 { BITS_EOT } 248 }}, 249 250 { 0xC001001D, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM2 Register", "This register indicates the Top of Memory above 4GB", { 251 { 63, 24, RESERVED }, 252 { 39, 8, "TOM2 39-32", "", PRESENT_HEX, { 253 { BITVAL_EOT } 254 }}, 255 { 31, 9, "TOM2 31-23", "", PRESENT_HEX, { 256 { BITVAL_EOT } 257 }}, 258 { 22, 23, RESERVED }, 259 { BITS_EOT } 260 }}, 261 262 { 0xC0010016, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase0", "This register holds the base of the variable I/O range", { 263 { 63, 24, RESERVED }, 264 { 39, 8, "BASE 27-20", "", PRESENT_HEX, { 265 { BITVAL_EOT } 266 }}, 267 { 31, 20, "BASE 20-0", "", PRESENT_HEX, { 268 { BITVAL_EOT } 269 }}, 270 { 11, 6, RESERVED }, 271 { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { 272 { MSR1(0), "RdDram disabled" }, 273 { MSR1(1), "RdDram enabled" }, 274 { BITVAL_EOT } 275 }}, 276 { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { 277 { MSR1(0), "WrDram disabled" }, 278 { MSR1(1), "WrDram enabled" }, 279 { BITVAL_EOT } 280 }}, 281 { BITS_EOT } 282 }}, 283 284 { 0xC0010017, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", { 285 { 63, 24, RESERVED }, 286 { 39, 8, "MASK 27-20", "", PRESENT_HEX, { 287 { BITVAL_EOT } 288 }}, 289 { 31, 20, "MASK 20-0", "", PRESENT_HEX, { 290 { BITVAL_EOT } 291 }}, 292 { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { 293 { MSR1(0), "V I/O range disabled" }, 294 { MSR1(1), "V I/O range enabled" }, 295 { BITVAL_EOT } 296 }}, 297 { 10, 11, RESERVED }, 298 { BITS_EOT } 299 }}, 300 301 { 0xC0010018, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase1", "This register holds the base of the variable I/O range", { 302 { 63, 24, RESERVED }, 303 { 39, 8, "BASE 27-20", "", PRESENT_HEX, { 304 { BITVAL_EOT } 305 }}, 306 { 31, 20, "BASE 20-0", "", PRESENT_HEX, { 307 { BITVAL_EOT } 308 }}, 309 { 11, 6, RESERVED }, 310 { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { 311 { MSR1(0), "RdDram disabled" }, 312 { MSR1(1), "RdDram enabled" }, 313 { BITVAL_EOT } 314 }}, 315 { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { 316 { MSR1(0), "WrDram disabled" }, 317 { MSR1(1), "WrDram enabled" }, 318 { BITVAL_EOT } 319 }}, 320 { BITS_EOT } 321 }}, 322 323 { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask1", "This register holds the mask of the variable I/O range", { 324 { 63, 24, RESERVED }, 325 { 39, 8, "MASK 27-20", "", PRESENT_HEX, { 326 { BITVAL_EOT } 327 }}, 328 { 31, 20, "MASK 20-0", "", PRESENT_HEX, { 329 { BITVAL_EOT } 330 }}, 331 { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { 332 { MSR1(0), "V I/O range disabled" }, 333 { MSR1(1), "V I/O range enabled" }, 334 { BITVAL_EOT } 335 }}, 336 { 10, 11, RESERVED }, 337 { BITS_EOT } 338 }}, 339 340 { MSR_EOT } 341 };