debug_cb_405.cmm
1 ;============================================================================ 2 ;## SPDX-License-Identifier: GPL-2.0-only 3 ;============================================================================ 4 ; Name: 5 ; debug_cb_405.cmm 6 ; 7 ; Description: 8 ; Debug coreboot 405 front-end 9 ;============================================================================ 10 11 ;============================================================================ 12 ; CMM script variables 13 ;============================================================================ 14 15 LOCAL &TargetPkg 16 17 GLOBAL &BBEntryAddr // Bootblock Entry 18 GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec 19 GLOBAL &VEREntryAddr // Verstage Entry 20 GLOBAL &ROMEntryAddr // Romstage Entry 21 GLOBAL &QCLEntryAddr // QCLstage Entry 22 GLOBAL &RAMEntryAddr // Ramstage Entry 23 GLOBAL &BL31EntryAddr // BL31 Entry 24 GLOBAL &DCEntryAddr // Depthcharge Entry 25 GLOBAL &KernelEntryAddr // Kernel Entry 26 27 GLOBAL &PreRamConsoleAddr 28 GLOBAL &RamConsoleAddr 29 GLOBAL &PreRamCbfsCache 30 GLOBAL &VBoot2Work 31 GLOBAL &Stack 32 GLOBAL &Ttb 33 GLOBAL &Timestamp 34 GLOBAL &CbmemTop 35 GLOBAL &PostRamCbfsCache 36 37 GLOBAL &CBTablePtr 38 39 GLOBAL &debug 40 41 ;============================================================================ 42 43 ;--------------------------------------------------- 44 ; Entry point 45 ;--------------------------------------------------- 46 ENTRY &ImageName 47 48 // Later these can be parameterized 49 &TargetPkg="Qcs405Pkg" 50 51 // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld 52 &BBEntryAddr=0x8c2f000 53 &VEREntryAddr=0x8C00000 54 &ROMEntryAddr=0x8C00000 55 &QCLEntryAddr=0x1485AC00 56 &RAMEntryAddr=0x9F860000 57 &BL31EntryAddr=0x06820000 58 &DCEntryAddr=0xf1104800 59 &KernelEntryAddr=0x90080000 60 61 &PreRamConsoleAddr=0x8C4F400 62 &VBoot2Work=0x8C47000 63 &Stack=0x8C4B000 64 &Ttb=0x8C39000 65 &Timestamp=0x8C4F000 66 &PreRamCbfsCache=0x8C57400 67 &CbmemTop=0x280000000 68 &PostRamCbfsCache=0x9F800000 69 // End of memlayout.ld settings 70 71 // Common commands irrespective of &Mode 72 PATH 73 &CwDir=os.pwd() 74 PATH + &CwDir 75 76 // position at top of coreboot tree 77 // find depth count for source loading 78 cd ..\..\..\.. 79 &srcpath=os.pwd() 80 81 b.sel PROGRAM onchip 82 ;sys.u 83 84 b.d /all 85 86 ;go &BBEntryAddr 87 ;wait !run() 88 89 ;--------------------------------------------------- 90 ; Setup area and log 91 ;--------------------------------------------------- 92 area.clear 93 area.reset 94 area.create CB_Logs 1000. 8192. 95 area.select CB_Logs 96 97 ;winclear 98 ;b.d /all 99 100 if FILE.EXIST("C:\TEMP\WIN.CMM") 101 do C:\TEMP\WIN.CMM 102 103 area.view CB_Logs 104 105 PRINT %String "Source Path: &srcpath" 106 107 symbol.sourcepath.setbasedir &srcpath\src 108 109 PRINT "pbl32_to_bootblock64 jump" 110 do pbl32_to_bootblock64_jump.cmm 111 do clear_bss.cmm 112 WAIT 5s 113 b 114 115 // Make parsing simple, upper-case parameters 116 &Imagename=STRING.UPR("&Imagename") 117 IF (STR.CP("&ImageName","DEBUG,*")) 118 ( 119 &debug="DEBUG" 120 ) 121 ELSE 122 ( 123 &debug="" 124 ) 125 &Imagename=STR.CUT("&ImageName",6) 126 IF "&debug"=="" 127 ( 128 PRINT "SPI_RAM LOAD" 129 &ImageName=STRING.UPR("&ImageName") 130 IF "&ImageName"=="" 131 ( 132 &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC 133 ) 134 PRINT "&ImageName" 135 ) 136 ELSE 137 ( 138 if (STR.CP("&debug","DEBUG")) 139 ( 140 PRINT "DEBUG" 141 &ImageName=STRING.UPR("&ImageName") 142 IF "&ImageName"=="" 143 ( 144 &ImageName="RAM,ALL" //for RAM loading all the images 145 ) 146 PRINT "&ImageName" 147 ) 148 ) 149 150 DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName 151 152 enddo