/ wordpr.vhd
wordpr.vhd
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 -- 6 -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics 7 -- http://www.mesanet.com 8 -- 9 -- This program is is licensed under a disjunctive dual license giving you 10 -- the choice of one of the two following sets of free software/open source 11 -- licensing terms: 12 -- 13 -- * GNU General Public License (GPL), version 2.0 or later 14 -- * 3-clause BSD License 15 -- 16 -- 17 -- The GNU GPL License: 18 -- 19 -- This program is free software; you can redistribute it and/or modify 20 -- it under the terms of the GNU General Public License as published by 21 -- the Free Software Foundation; either version 2 of the License, or 22 -- (at your option) any later version. 23 -- 24 -- This program is distributed in the hope that it will be useful, 25 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 26 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 -- GNU General Public License for more details. 28 -- 29 -- You should have received a copy of the GNU General Public License 30 -- along with this program; if not, write to the Free Software 31 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 32 -- 33 -- 34 -- The 3-clause BSD License: 35 -- 36 -- Redistribution and use in source and binary forms, with or without 37 -- modification, are permitted provided that the following conditions 38 -- are met: 39 -- 40 -- * Redistributions of source code must retain the above copyright 41 -- notice, this list of conditions and the following disclaimer. 42 -- 43 -- * Redistributions in binary form must reproduce the above 44 -- copyright notice, this list of conditions and the following 45 -- disclaimer in the documentation and/or other materials 46 -- provided with the distribution. 47 -- 48 -- * Neither the name of Mesa Electronics nor the names of its 49 -- contributors may be used to endorse or promote products 50 -- derived from this software without specific prior written 51 -- permission. 52 -- 53 -- 54 -- Disclaimer: 55 -- 56 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 59 -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 60 -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 61 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 62 -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 63 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 64 -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 66 -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 -- POSSIBILITY OF SUCH DAMAGE. 68 -- 69 70 entity wordpr is 71 generic ( 72 size : integer; 73 buswidth : integer 74 ); 75 port ( 76 clear: in STD_LOGIC; 77 clk: in STD_LOGIC; 78 ibus: in STD_LOGIC_VECTOR (buswidth-1 downto 0); 79 obus: out STD_LOGIC_VECTOR (buswidth-1 downto 0); 80 loadport: in STD_LOGIC; 81 loadddr: in STD_LOGIC; 82 loadaltdatasrc: in STD_LOGIC; 83 loadopendrainmode: in STD_LOGIC; 84 loadinvert: in STD_LOGIC; 85 readddr: in STD_LOGIC; 86 portdata: out STD_LOGIC_VECTOR (size-1 downto 0); 87 altdata: in STD_LOGIC_VECTOR (size-1 downto 0) 88 ); 89 end wordpr; 90 91 architecture behavioral of wordpr is 92 93 signal outreg: std_logic_vector (size-1 downto 0); 94 signal ddrreg: std_logic_vector (size-1 downto 0):= (others => '0'); 95 signal tsoutreg: std_logic_vector (size-1 downto 0); 96 signal opendrainsel: std_logic_vector (size-1 downto 0):= (others => '0'); 97 signal altdatasel: std_logic_vector (size-1 downto 0):= (others => '0'); 98 signal invertsel: std_logic_vector (size-1 downto 0):= (others => '0') ; 99 signal tdata: std_logic_vector (size-1 downto 0); 100 signal tddr: std_logic_vector (size-1 downto 0); 101 102 begin 103 awordioport: process ( 104 clk, 105 ibus, 106 loadport, 107 loadddr, 108 readddr, 109 outreg, 110 ddrreg, 111 altdatasel, 112 invertsel, 113 altdata, 114 tdata, 115 tsoutreg, 116 opendrainsel) 117 begin 118 if rising_edge(clk) then 119 if loadport = '1' then 120 outreg <= ibus(size-1 downto 0); 121 end if; 122 if loadddr = '1' then 123 ddrreg <= ibus(size-1 downto 0); 124 end if; 125 if loadaltdatasrc = '1' then 126 altdatasel <= ibus(size-1 downto 0); 127 end if; 128 if loadopendrainmode = '1' then 129 opendrainsel <= ibus(size-1 downto 0); 130 end if; 131 if loadinvert = '1' then 132 invertsel <= ibus(size-1 downto 0); 133 end if; 134 if clear = '1' then 135 ddrreg <= (others => '0'); 136 opendrainsel <= (others => '0'); 137 end if; 138 end if; -- clk 139 140 for i in 0 to size-1 loop 141 if altdatasel(i) = '0' then 142 if invertsel(i) = '0' then -- normal output data, normal outputs can be inverted 143 tdata(i) <= outreg(i); 144 else 145 tdata(i) <= not outreg(i); 146 end if; 147 else 148 if invertsel(i) = '0' then -- alternate output data, alternate outputs can be inverted 149 tdata(i) <= altdata(i); 150 else 151 tdata(i) <= not altdata(i); 152 end if; 153 end if; 154 if opendrainsel(i) = '0' then -- normal DDR 155 if ddrreg(i) = '1' then 156 tsoutreg(i) <= tdata(i); 157 else 158 tsoutreg(i) <= 'Z'; 159 end if; 160 else 161 if tdata(i) = '0' then -- open drain option = active pulldown 162 tsoutreg(i) <= '0'; 163 else 164 tsoutreg(i) <= 'Z'; 165 end if; 166 end if; 167 end loop; 168 169 portdata <= tsoutreg; 170 obus <= (others => 'Z'); 171 if readddr = '1' then 172 obus(size-1 downto 0) <= ddrreg; 173 obus(buswidth -1 downto size) <= (others => '0'); 174 end if; 175 176 end process; 177 end behavioral;