1  /* ----------------------------------------------------------------------
  2   * Project:      CMSIS DSP Library
  3   * Title:        arm_and_u32.c
  4   * Description:  uint32_t bitwise AND
  5   *
  6   * $Date:        23 April 2021
  7   * $Revision:    V1.9.0
  8   *
  9   * Target Processor: Cortex-M and Cortex-A cores
 10   * -------------------------------------------------------------------- */
 11  /*
 12   * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
 13   *
 14   * SPDX-License-Identifier: Apache-2.0
 15   *
 16   * Licensed under the Apache License, Version 2.0 (the License); you may
 17   * not use this file except in compliance with the License.
 18   * You may obtain a copy of the License at
 19   *
 20   * www.apache.org/licenses/LICENSE-2.0
 21   *
 22   * Unless required by applicable law or agreed to in writing, software
 23   * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 24   * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 25   * See the License for the specific language governing permissions and
 26   * limitations under the License.
 27   */
 28  
 29  #include "dsp/basic_math_functions.h"
 30  
 31  /**
 32    @ingroup groupMath
 33   */
 34  
 35  /**
 36    @addtogroup And
 37    @{
 38   */
 39  
 40  /**
 41    @brief         Compute the logical bitwise AND of two fixed-point vectors.
 42    @param[in]     pSrcA      points to input vector A
 43    @param[in]     pSrcB      points to input vector B
 44    @param[out]    pDst       points to output vector
 45    @param[in]     blockSize  number of samples in each vector
 46    @return        none
 47   */
 48  
 49  void arm_and_u32(
 50      const uint32_t * pSrcA,
 51      const uint32_t * pSrcB,
 52            uint32_t * pDst,
 53            uint32_t blockSize)
 54  {
 55      uint32_t blkCnt;      /* Loop counter */
 56  
 57  #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
 58      uint32x4_t vecSrcA, vecSrcB;
 59  
 60      /* Compute 4 outputs at a time */
 61      blkCnt = blockSize >> 2;
 62  
 63      while (blkCnt > 0U)
 64      {
 65          vecSrcA = vld1q(pSrcA);
 66          vecSrcB = vld1q(pSrcB);
 67  
 68          vst1q(pDst, vandq_u32(vecSrcA, vecSrcB) );
 69  
 70          pSrcA += 4;
 71          pSrcB += 4;
 72          pDst  += 4;
 73  
 74          /* Decrement the loop counter */
 75          blkCnt--;
 76      }
 77  
 78      /* Tail */
 79      blkCnt = blockSize & 3;
 80  
 81      if (blkCnt > 0U)
 82      {
 83          mve_pred16_t p0 = vctp32q(blkCnt);
 84          vecSrcA = vld1q(pSrcA);
 85          vecSrcB = vld1q(pSrcB);
 86          vstrwq_p(pDst, vandq_u32(vecSrcA, vecSrcB), p0);
 87      }
 88  #else
 89  #if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
 90      uint32x4_t vecA, vecB;
 91  
 92      /* Compute 4 outputs at a time */
 93      blkCnt = blockSize >> 2U;
 94  
 95      while (blkCnt > 0U)
 96      {
 97          vecA = vld1q_u32(pSrcA);
 98          vecB = vld1q_u32(pSrcB);
 99  
100          vst1q_u32(pDst, vandq_u32(vecA, vecB) );
101  
102          pSrcA += 4;
103          pSrcB += 4;
104          pDst  += 4;
105  
106          /* Decrement the loop counter */
107          blkCnt--;
108      }
109  
110      /* Tail */
111      blkCnt = blockSize & 3;
112  #else
113      /* Initialize blkCnt with number of samples */
114      blkCnt = blockSize;
115  #endif
116  
117      while (blkCnt > 0U)
118      {
119          *pDst++ = (*pSrcA++)&(*pSrcB++);
120  
121          /* Decrement the loop counter */
122          blkCnt--;
123      }
124  #endif /* if defined(ARM_MATH_MVEI) */
125  }
126  
127  /**
128    @} end of And group
129   */